Design Verification Engineering

Etched is building the world’s first AI inference system purpose-built for transformers - delivering over 10x higher performance and dramatically lower cost and latency than a B200. With Etched ASICs, you can build products that would be impossible with GPUs, like real-time video generation models and extremely deep & parallel chain-of-thought reasoning agents. We are seeking a Design Verification Engineer to join our Internal IP DV team. You will ensure the custom IPs powering Sohu — including systolic arrays, DMA engines, and NoCs — are robust, high-performance, and silicon-ready. You will collaborate with architects, RTL designers, and SW/FW/emulation teams to validate correctness and performance across the full hardware-software stack.

Develop and maintain UVM/SystemVerilog testbenches for high-performance IPs (compute arrays, DMAs, NoCs, memory subsystems).

Define and execute verification plans covering functional correctness, corner cases, concurrency, and performance bottlenecks.

Work closely with architects and designers to validate functionality and design intent.

Strong debugging and problem-solving skills for complex digital designs.

Solid knowledge of computer architecture and digital design fundamentals.

Experience verifying systolic arrays, DMA engines, or NoC/AXI protocols.

Scripting skills (Python/Perl/TCL or similar) for automation, debug and regression flows.

Medical, dental, and vision packages with generous premium coverage

$500 per month credit for waiving medical benefits

Housing subsidy of $2k per month for those living within walking distance of the office

Relocation support for those moving to San Jose (Santana Row)

Daily lunch + dinner in our office

We think most of the progress in the AI field has come from using more FLOPs to train and run models, and the best way to get more FLOPs is to build model‑specific hardware. Larger and larger training runs encourage companies to consolidate around fewer model architectures, which creates a market for single‑model ASICs.

We are a fully in‑person team in San Jose (Santana Row), and greatly value engineering skills. We do not have boundaries between engineering and research, and we expect all of our technical staff to contribute to both as needed.

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