Design Verification Engineering

About the RoleJoin our Logic Design and Validation group within the Design Technology Platforms department, where you'll play a key role in shaping the future of semiconductor technology. You'll be part of a dynamic team responsible for developing RTL models and pre-silicon validation tests for test chips on next-generation silicon manufacturing processes. This is an opportunity to work at the cutting edge of chip design, collaborating across multidisciplinary teams to deliver robust, high-quality silicon.Define Verification Strategy - Own and drive comprehensive verification plans for complex digital systems, ensuring thorough coverage closure across multiple projects.Assertion-Based Verification - Create and apply SystemVerilog Assertions (SVA) to strengthen coverage closure and improve overall verification quality.Debug & Root Cause Analysis - Identify, debug, and resolve pre-silicon failures, implementing corrective measures and driving issues to closure.Cross-Team Collaboration - Partner with architecture, physical design, and post-silicon teams to continuously improve verification strategies for complex architectural features.Documentation & Reviews - Maintain detailed test plans and lead technical reviews with design and architecture teams.Strong analytical and troubleshooting skills with a structured approach to problem-solving.Minimum qualifications listed below would be obtained through a combination of industry relevant job experience, internship experience and / or schoolwork/classes/research. Minimum QualificationsOption A: Master's degree in Electrical Engineering, Computer Engineering, or a STEM-related field with a minimum of 1+ years of relevant experience.Option B: Bachelor's degree in Electrical Engineering, Computer Engineering, or a STEM-related field with a minimum of 3+ years of relevant experience.Experience in Digital design using Verilog and/or SystemVerilog.Experience with pre-silicon validation closure across multiple projects.Hands-on experience with UVM testbench design, with a focus on reusability and scalability.Experience with end-to-end validation strategies for complex digital systems.Scripting proficiency in Python, Perl, or TCL for design and verification automation.Experience with AI/ML techniques and their application in verification automation and efficiency.Shift 1 (United States of America)Primary Location: US, Oregon, HillsboroAdditional Locations:US, California, FolsomPosting Statement:All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.It consists of competitive pay, stock bonuses, and benefit programs which include health, retirement, and vacation. Annual Salary Range for jobs which could be performed in the US: $105,650.00-200,340.00 USDThe range displayed on this job posting reflects the minimum and maximum target compensation for the position across all US locations. Within the range, individual pay is determined by work location and additional factors, including job-related skills, experience, and relevant education or training. Work Model for this RoleThis role will be eligible for our hybrid work model which allows employees to split their time between working on-site at their assigned Intel site and off-site. * Candidates should never be required to pay recruitment fees, medical examination fees, or any other charges as a condition of employment. If you are asked to pay any fees during our hiring process, please report this immediately to your recruiter.US, California, FolsomType: Full time