Validation Engineering

Role: PCIe Silicon Validation & Debug Engineer
Duration: 9+ Months Contract

We are seeking a skilled PCIe Engineer to join our Silicon Engineering team. The ideal candidate will have deep expertise in PCI Express (PCIe) interfaces and protocols, with hands-on experience in test development, analysis, and debug across both pre-silicon and post-silicon environments. You will play a critical role in ensuring the functional correctness, performance, and compliance of PCIe IP and SoC-level interconnects.

Create directed and constrained-random tests targeting PCIe Transaction Layer (TLP), Data Link Layer (DLLP), and Physical Layer (PHY) functionality
Perform protocol-level analysis using VIP (Verification IP) environments and bus functional models
Debug RTL-level issues related to link training, power management (ASPM, L-states), equalization, and error handling
Bring up and validate PCIe links on silicon platforms (FPGA, emulation, and first silicon)
Develop and execute post-silicon validation test plans covering link training, enumeration, data integrity, error injection, and compliance
Perform root-cause analysis of PCIe link failures, packet errors, and performance degradation
Characterize PCIe PHY performance including jitter, eye diagrams, and signal integrity
Collaborate with platform, firmware, and BIOS teams to resolve system-level PCIe issues
Drive compliance and interoperability testing per PCI-SIG specifications

Document findings, debug methodologies, and test coverage metrics
D. in Electrical Engineering, Computer Engineering, or related field
Data Link Layer: ACK/NAK, replay, LCRC, DLLP
Physical Layer: Link training (LTSSM), equalization, encoding (8b/10b, 128b/130b)
Familiarity with scripting languages (Python, Perl, Tcl) for test automation and log parsing
Solid understanding of PCIe enumeration, BAR programming, and configuration space
Experience with FPGA prototyping or emulation platforms is a plus

Knowledge of signal integrity concepts (S-parameters, eye diagrams, jitter analysis)
Familiarity with compliance testing per PCI-SIG specifications and test suites