Urgent: Senior Architect

The CEG NAG (Networking Architecture Group) is Intel's premier team focused on defining the future of high-performance networking silicon. Our team architects next-generation networking solutions that enable hyperscale data centers, cloud infrastructure, and AI workloads to achieve unprecedented performance and efficiency. We specialize in IPU/DPU platforms, advanced packet processing architectures, and programmable networking technologies that form the backbone of modern distributed computing systems.
We are seeking a Senior SoC Compute/Memory Subsystem Architect to define and drive the architecture of compute complexes and high-performance memory subsystems for next-generation IPU/DPU platforms.
This role is responsible for end-to-end architecture of CPU clusters, cache hierarchies, coherency models, and memory subsystems. You will optimize system-level performance, scalability, power efficiency, and programmability while ensuring seamless interaction with networking, storage, and accelerator subsystems in hyperscale environments.
Compute Subsystem Architecture

• Define architecture for IPU compute complexes (e.g., ARM/x86 clusters), including core selection, scaling strategy, and configuration tradeoffs
• Architect compute subsystem roles (control plane, data plane assist, offload execution, management services)
• Drive compute architecture decisions balancing performance, power, and area

Cache Hierarchy and Coherency Architecture

• Define and evolve multi-level cache hierarchy (private/shared caches, system-level cache)
• Architect coherency models across compute cores, accelerators, and IO subsystems (coherent vs non-coherent interactions)
• Memory Subsystem Architecture

# Architect system memory subsystems including:

Memory controllers and scheduling policies
Work with Performance architect in define memory access models for compute, network, and accelerator subsystems

• IO Memory and Virtualization Architecture (SMMU/IOMMU)
• Define architecture for SMMU/IOMMU supporting virtualization-heavy IPU workloads

# Architect features such as:

System-Level Integration (Compute Network Storage)
# Architect integration between:

Network subsystem (packet processing pipelines)
Optimize data movement across subsystems to minimize copies, latency, and bandwidth overhead.
# Drive system architecture decisions for balanced SoC performance.

Architect mechanisms for:

Optimize performance-per-watt at system level.

Multi-Generation Architecture Roadmap
# Networking subsystem (NSS)
Validation and performance modeling and testing
# Drive architecture alignment and resolve cross-domain tradeoff

Ability to define long-term architecture vision and align stakeholders
Approaches complex system challenges with structured thinking
Builds strong partnerships across engineering disciplines
Customer-focused mindset: For information on Intel’s immigration sponsorship guidelines, please see
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Batchelor's degree in Electrical Engineering, Computer Engineering, or in a STEM related Field of Study.
SoC / CPU / memory subsystem architectureCPU architecture and cache hierarchies
Memory subsystems (DDR/HBM, controllers, QoS)Coherent/Non-Coherent interconnect architectures
Experience in system-level performance and PPA tradeoff analysis
Drive architecture definition from concept to silicon
Post Graduate degree in Electrical Engineering, Computer Engineering, or in a STEM related Field of Study
ARM and x86 compute and memory subsystem experience, including NUMA systems, cache coherency, or large scale platform architectures.
Experience with IPU / SmartNIC or accelerator centric SoCs, particularly in cloud and hyperscale environments
Familiarity with PCIe, CXL, and memory semantics for high performance IO.
Join us in building a brighter future through technology innovation!
Shift:
Shift 1 (United States of America)
The Central Engineering Group (CEG) is Intel's data-driven organization that builds scalable engineering solutions across three pillars: Product Enablement (IP, tools, and methodologies), Custom ASIC (leveraging existing IP for custom silicon), and Foundry Enablement (supporting top customers and validating technologies). The team focuses on customer-driven, end-to-end solutions with short development cycles to deliver measurable business impact across Intel's product and foundry businesses.
All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.
It consists of competitive pay, stock bonuses, and benefit programs which include health, retirement, and vacation. The range displayed on this job posting reflects the minimum and maximum target compensation for the position across all US locations. Within the range, individual pay is determined by work location and additional factors, including job-related skills, experience, and relevant education or training. This role will be eligible for our hybrid work model which allows employees to split their time between working on-site at their assigned Intel site and off-site. * The application window for this job posting is expected to end by 07/31/2026
Candidates should never be required to pay recruitment fees, medical examination fees, or any other charges as a condition of employment. If you are asked to pay any fees during our hiring process, please report this immediately to your recruiter.