Design Verification Engineering
Varite Inc
The project relates to the design and verification of a custom controller for analog components. The controller has interfaces such as SPI, Ethernet and AXI to driven the internal components and send data.
As a UVM/ SystemVerilog Design Verification Engineer, you will own functional verification for a custom controller.
You will develop functional verification infrastructure to ensure functional correctness of a design as well as improve the throughput of the verification effort.
In this role, you will develop test plans for functional units and subsystems.
You will analyze coverage from various dimensions and develop monitors and checkers for better quality assurance. UVM/python test development for driving VIPs and other stimulus drivers.
Generation of test components such as monitors, scoreboards and python models.
Coverage closure and GLS bringup and testing.
8 years of experience with verification methodologies and languages such as UVM and SystemVerilog.
- High proficiency in python would be a plus.
- Knowledge of general-purpose operating systems such as Linux and Android would be a plus.
- Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field, or equivalent practical experience.
About US Tech Solutions:
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All qualified applicants will receive consideration for employment without regard to race, color, religion, sex, sexual orientation, gender identity, national origin, disability, or status as a protected veteran.
Vacancy posted 2 days ago
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