Architecture / design / development - architect

Job Description Join the leading chiplet startup! As an Eliyan NuLink PHY IO Architect, you will be working at a fast-paced early-stage startup creating technologies that fuel tomorrow’s chiplet based systems with best-in-class power, area, manufacturability, and design flexibility. You will drive the definition and development of cutting-edge ASICs from RTL to GDSII. You will work with a cross-functional team of industry experts that operate from first principles, innovate, and push the envelope to create high-volume and high-performance manufacturable products. In this role, you will own the architecture, oversee design and validation, and be a focal point for customer and marketing team interactions. You will also focus on developing and improving design flows and methodologies to ensure high-quality, on-time delivery. Architecture: Definition of a firmware first based hardware architecture approach.
Performance Evaluation and Optimization: Model and tune PHY data path, link protocols, and CDC architectures for protocol efficiency, bandwidth, latency, power, and signal integrity. Conduct technical evaluation and benchmark analysis against internal and external IPs.
Support customer integration for compute-to-memory (CXL/DDR), processor interconnect (AXI/PCIe), and control plane (APB). Create clear and comprehensive architecture specifications with foolproof integration guidelines.
Validation: Review characterization plans for PLL, VCO, ATB, and link training. Be part of industry standards bodies and work groups to keep Eliyan's product implementations up to date with the latest versions of the standards.
Leadership: Mentor engineers on protocol implementation, timing constraints, and hierarchical design. Effectively collaborate with industry technologists, business leaders and ability to network seamlessly with industry peers to influence stakeholders.

Expertise in multiple areas of architecture definition, chip micro-architecture, protocol definition and implementation

• Bachelor’s or Master’s degree in Electrical Engineering, Computer Engineering, or a related field
• 15+ years of experience in ASIC architecture with strong bias for practical logic design and influence of physical implementation, with a proven track record of leading teams through successful tapeouts
• Performance modeling of hardware implementations with high level languages like C, C++ or SystemC
• Adept at clocking and floorplan guidelines for PHY implementation
• We may use artificial intelligence (AI) tools to support parts of the hiring process, such as reviewing applications, analyzing resumes, or assessing responses and identifying potential inconsistencies or verification signals in application materials based on available information. If you would like more information about how your data is processed, please contact us.