Design tech - engineering

SpaceX was founded under the belief that a future where humanity is out exploring the stars is fundamentally more exciting than one where we are not. Today SpaceX is actively developing the technologies to make this possible, with the ultimate goal of enabling human life on Mars.PHYSICAL DESIGN ENGINEER (SILICON ENGINEERING)At SpaceX we’re leveraging our experience in building rockets and spacecraft to deploy Starlink, the world’s most advanced broadband internet system. Starlink is the world’s largest satellite constellation and is providing fast, reliable internet to millions of users worldwide. We design, build, test, and operate all parts of the system - thousands of satellites, consumer receivers that allow users to connect within minutes of unboxing, and the software that brings it all together. We’ve only begun to scratch the surface of Starlink’s potential global impact and are looking for best-in-class engineers to help maximize Starlink’s utility for communities and businesses around the globe. We are seeking a motivated, proactive, and intellectually curious engineer who will work alongside world-class cross-disciplinary teams (systems, firmware, architecture, design, validation, product engineering, ASIC implementation). In this role, you will be developing cutting-edge next-generation ASICs for deployment in space and ground infrastructures around the globe. Your efforts will help deliver cutting-edge solutions that will expand the performance and capabilities of the Starlink network.RESPONSIBILITIES: Perform partition synthesis and physical implementation steps (e.g. synthesis, floorplanning, power/ground grid generation, place and route, timing, noise, physical verification, electromigration, voltage drop, logic equivalency and other signoff checks)Develop/improve physical design methodologies and automation scripts for various implementation stepsClosely collaborate with the ASIC design team to drive architectural feasibility studies, develop timing, power and area design targets, and explore RTL/design tradeoffsResolve design/timing/congestion and flow issues, identify potential solutions and drive executionRun, debug, and fix signoff closure issues in static timing analysis (STA), noise, logic equivalency, physical verification, electromigration and voltage dropBASIC QUALIFICATIONS:Bachelor’s degree in electrical engineering, computer engineering or computer science1+ years of professional experience working on RTL2GDSII physical design and/or physical design flow developmentPREFERRED SKILLS AND EXPERIENCE:Experience with industry standard EDA tools including understanding of their capabilities and underlying algorithmsKnowledge of deep sub-micron FinFET and CMOS solid state physicsUnderstanding of CMOS digital design principles, basic standard cells their functionality, standard cell librariesUnderstanding of CMOS power dissipation in deep submicron processes leakage/dynamicFamiliar with CMOS analog circuit and physical designBasic knowledge of DFT/Scan/MBIST/LBIST and understanding of their impact on physical design flowsGood scripting skills (csh/bash, Perl, Python, TCL, Makefile etc.)Ability to work extended hours and weekends as needed to meet critical project milestonesITAR REQUIREMENTS:S. citizen or national, (ii) U.S. lawful, permanent resident (aka green card holder), (iii) Refugee under 8 U.employment with SpaceX is governed on the basis of merit, competence and qualifications and will not be influenced in any manner by race, color, religion, gender, national origin/ethnicity, veteran status, disability status, age, sexual orientation, gender identity, marital status, mental or physical disability or any other legally protected status.Applicants wishing to view a copy of SpaceX’s Affirmative Action Plan for veterans and individuals with disabilities, or applicants requiring reasonable accommodation to the application/interview process should reach out to View email address on click.appcast.io.