Senior Digital Design Engineering

Senior or Staff Digital Design Engineer Reports To: Head of Engineering

Powerlattice is a well-funded semiconductor start-up company backed by leading Silicon Valley venture capital firms. We are developing groundbreaking chiplet power delivery technology that will transform how high-performance processors are powered, enabling the next generation of AI and advanced computing.

We are seeking an experienced and hands-on Senior Digital Design Engineer to contribute to the design and implementation of complex digital systems and SoC components. This role offers the opportunity to own significant functional blocks from microarchitecture through RTL development, integration, and implementation while collaborating closely with verification, physical design, and DFT teams.

The ideal candidate is passionate about digital design, enjoys solving challenging technical problems, and thrives in a collaborative startup environment where individual contributions have a direct impact on product success.

Digital Design & RTL Development

Develop microarchitecture for assigned digital blocks and subsystems

Design, code, and maintain high-quality, synthesizable RTL

Evaluate design tradeoffs involving performance, power, area (PPA), and testability

Participate in design reviews and incorporate feedback into RTL implementation

Integration & Implementation

Support lint, CDC/RDC, synthesis, and design quality checks

Collaborate with physical design teams to resolve implementation issues

Support logic equivalence checking (LEC) and implementation debugging

Design Quality

Analyze and resolve design issues throughout the development lifecycle

Work closely with verification, DFT, physical implementation, firmware, and systems teams

Partner with architects and senior technical leaders to refine design requirements

Contribute to continuous improvement of design methodologies and development processes

This is a Hybrid role requiring 3 days a week onsite at our HQ’s in Vancouver, WA (Greater Portland Area) or Chandler, AZ. While we are primarily seeking candidates in HQ-Vancouver and Chandler, remote flexibility may be considered for exceptional candidates in Silicon Valley, CA.

• Bachelor's or Master's degree in Electrical Engineering, Computer Engineering, or a related discipline
• 6+ years of digital IC design experience
• Experience designing digital blocks for complex SoCs or ASICs
• RTL design and microarchitecture
• Synthesis and physical implementation considerations
• Familiarity with static timing analysis (STA)

Exposure to advanced semiconductor process nodes

Stock option grant

Comprehensive benefits package including health, dental, vision, and 401(k)