Senior DFT Architect - Multi-Chip SOC
Eridu Corp.
Eridu Corp., a Silicon Valley hardware startup, seeks a senior EE to define the DFT architecture for a multi-chip SOC, encompassing test design functions such as Scan, BIST, Memory Repair, and advanced DFT techniques. You will work with a world-class engineering team, require 15+ years of EE experience, fluency in Verilog/SystemVerilog, RTL and gate-level simulation, and proficiency with Mentor or Synopsys test tools. The role is based in Saratoga, CA with a competitive base salary. #J-18808-Ljbffr Eridu Corp.
Vacancy posted 4 days ago
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