RTL Design Intern — Verilog/ML Hardware, 12‑week Paid
Etched
Etched is seeking an RTL Intern based in San Jose, CA, to assist in designing microarchitecture and implementing logic using Verilog. This 12-week paid internship offers generous housing support and includes daily meals in our office. Interns will receive mentorship from industry leaders while tackling significant challenges in modern machine learning. Ideal candidates should pursue a degree in electrical engineering or a related field, and familiarity with high-speed digital logic and verification is preferred. #J-18808-Ljbffr Etched
Vacancy posted 2 days ago
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