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FPGA Engineer

$200k

Optiver

At Optiver we pride ourselves on being real engineers, not just coders. Our engineers work closely with traders to identify the business problems we face and determine how they should be solved. We apply a disciplined and scientific approach. We engineer simple, well-architected solutions that meet the dynamic needs of our traders. Our passion is to solve problems which really matter to the business, and we take pride in the quality of our solutions.Hardware Engineers at Optiver build hardware-based trading systems ranging from low latency algorithms to high bandwidth computation. They are responsible for owning all aspects of the development process from ideation to implementation creating bespoke solutions to our complex trading problems. Their systems have little room for failure which add to the stability of the market, not detract from it. Working in close collaboration with software engineers and traders, hardware engineers deeply understand our trading problems and create dynamic, well-architected systems that make an impact in a matter of days and weeks rather than months and years.What you’ll doAccelerate network infrastructure and trading system components with high-speed hardware designsResearch new low-latency techniques and platforms and identify opportunities for integration with our trading systemWork in a multidisciplinary team of traders, software developers, and infrastructure engineersLeverage the best hardware available or build in-house versions to ensure our FPGAs can interface with cutting edge server hardwareManage relationships with 3rd party vendorsWhat you’ll getYou’ll join a culture of collaboration and excellence, surrounded by curious thinkers and creative problem-solvers. Motivated by a passion for continuous improvement, you’ll thrive in a supportive, high-performing environment alongside talented colleagues, collectively tackling some of the toughest challenges in the financial markets.In addition, you’ll receive:The opportunity to work alongside best-in-class professionals from over 40 different countriesA highly competitive compensation packageGlobal profit-sharing pool and performance-based bonus structure401(k) match up to 50%Comprehensive health, mental, dental, vision, disability, and life coverage25 paid vacation days alongside market holidaysExtensive office perks, including breakfast, lunch and snacks, regular social events, clubs, sporting leagues and moreWho you areA Bachelor’s degree in CE, EE, CS, or related technical fieldExperience designing, coding, testing, and verifying FPGAs and/or ASICsExperience coding in VHDL, Verilog, SystemVerilog as well as C or C++Experience with RTL synthesis, writing timing, area, and other relevant constraintsExperience with digital simulators and self-checking test benchesExperience supporting post-silicon bring-up and debugging a plusAbility to work closely with software developers to rapidly deliver integrated systemsWho we areAt Optiver, our mission is to improve the market by injecting liquidity, providing accurate pricing, increasing transparency, and stabilizing the market no matter the conditions. With a focus on continuous improvement, we prioritize safeguarding the health and efficiency of the markets for all participants. As one of the largest market making institutions, we are a respected partner on 100+ exchanges across the globe.Our differences are our edge. Optiver does not discriminate on the basis of race, religion, color, sex, gender identity, sexual orientation, age, physical or mental disability, or other legally protected characteristics.Below is the expected base salary for this position. This is a good-faith estimate of the base pay scale for this position and offers will ultimately be determined based on experience, education, skill set, and performance in the interview process. This position will also be eligible for a discretionary bonus (if determined by Optiver) and Optiver’s benefits package with the benefits listed above. Base Salary Range$200,000—$200,000 USD

Vacancy posted 15 hours ago
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