Principal/Senior Staff Physical Design Engineer (Full-Chip SoC)

Job Title:  Principal/Senior Staff Physical Design Engineer

Location:  San Diego, CA or San Jose, CA

Employment Type:  Full-time/Direct

Industry:  Semiconductor

Compensation:  180k-225k

Schedule:  day time

About the Opportunity:

As a Physical Design Principal Engineer, you will be responsible for the entire SOC implementation and verification flow from RTL-to-GDS that includes floorplan, place and route, CTS, STA, PV/EMIR/Noise/SigEM cleanup and signoff on lower power SoC. You will be joining a team of engineers dedicated to pushing the envelope for a leading fabless wireless semiconductor platform company specializing in extreme low power wireless radio solutions. 

Why You'll Love Working Here:

*Supportive, team-driven culture that values collaboration, transparency, and accountability

*Opportunity to grow your career with a global workforce solutions leader serving multiple industries

*People-first environment that encourages employees to bring their authentic selves to work

*Strong focus on partnership, innovation, and delivering meaningful results for clients and candidates

Why This Opportunity is Exciting:

This role offers the chance to join a company that prioritizes both people and performance-where your contributions directly impact client success while giving you room to grow and develop professionally.

About Acara Solutions

Acara is a premier recruiting and workforce solutions provider-we help companies compete for talent. With a legacy of experience in various industries worldwide, we partner with clients, listen to their needs, and customize visionary talent solutions that drive desired business outcomes. We leverage decades of experience to deliver contingent staffing, direct placement, executive search, and workforce services worldwide.

Sound like a good fit?

What You'll Do:

• Complete entire physical implementation of the block and chip level
• Perform synthesis and physical implementation steps - synthesis, floor-planning, power delivery, place&route, timing noise, physical verification, IR/RV.
• Collaborate with the SOC design team to drive architectural feasibility studies, develop timing, power, and area design targets, and explore RTL/design tradeoffs
• Analyze the quality of the floorplan and Customized Clock tree structure and Place & Route
• Implement ECOs for timing closure
• Signal EM/Noise and Power IR/EM analysis and fix
• DRC/LVS/ERC/ANTENNA analysis and clean up
• Timing verification and signoff
• Physical verification and sign off

Job Requirements

What You'll Bring:

Master's Degree in Electrical Engineering or Computer Science

Minimum 8 years of Physical Design Engineering experience encompassing full-chip/SoC implementation and verification from RTL to GDS including floorplan, place & route, CTS and sign-off for lower power SoC

What Sets You Apart:

• Strong experience in Power/Ground grids, Partitioning, Timing ECO implementation, and physical verification.
• Netlist (or RTL)-GDS physical implementation experience
• In depth knowledge of major EDA tools/design flows
• Strong Cadence experience/background
• Experience with TSMC N22 or below technology
• Experience in chip integration and signoff
• Experience in Perl/TCL language programming

Additional Information:

After you , you may receive a call or message from our AI Talent Scout about this role or other opportunities that match your skills and preferences. AI agent role is to help speed up your hiring process by answering questions, confirming basic information, and identifying whether there's a mutual fit.

The call or chat may be recorded so that our recruiting team can review it - they make all final hiring decisions, while AI agent simply helps move you forward faster. The best part? They are available 24/7, so you can connect whenever it's convenient for you.

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Aleron companies (Acara Solutions, Aleron Shared Resources, Broadleaf Results, Lume Strategies, TalentRise, Viaduct) are an Equal Opportunity Employer. Race/Color/Gender/Religion/National Origin/Disability/Veteran.

Applicants for this position must be legally authorized to work in the United States. This position does not meet the employment requirements for individuals with F-1 OPT STEM work authorization status.