Principal Silicon Photonics Layout Engineer

About Us nEye.ai, a well-funded optical switch startup, is poised to revolutionize the future of data centers. nEye’s MEMS-based silicon photonics optical circuit switches (OCS) eliminate critical bottlenecks in AI processing by enabling direct optical connections among thousands of GPUs and memory units. The company's SuperSwitch is an ultra-low power consumption, high radix, compact chip-scale design, offering hyperscale data centers enhanced performance, efficiency, and scalability. Job Overview Principal Silicon Photonics Layout Engineer nEye is seeking a Principal Silicon Photonics Layout Engineer to actively lead the company’s design and tapeout of complex Photonic Integrated Circuits (PICs) using a code-based, functional layout methodology. In this role, you will be responsible for architecting and maintaining a robust script-based library of parametric components. You will bridge the gap between optical physics and software engineering, ensuring layouts are highly reproducible and optimized for high-yield, production-scale fabrication. This position is ideal for a candidate who treats layout as a software engineering challenge and thrives in a programmatic, automation-first environment. Responsibilities Functional Library Development: Architect and maintain a robust library of Python functions to generate parametric geometries. Production-Scale Layout: Execute full-chip assembly for high-volume manufacturing (HVM). Design for Test (DFT) Automation: Develop and implement automated functions for the insertion of optical/electrical test structures. Automated Routing: Develop scripts to automate complex optical routing and other design features via code. Physical Verification: Lead the DRC/LVS cleanup process using tools like Calibre or KLayout. Version Control & CI/CD: Utilize Git and “Layout CI” to manage the evolution of the function library and validate code changes. Required Skills Production SiPh Experience: 8-12+ years of experience in high-complexity layout design with a track record of shipping Silicon Photonics designs to production. Must understand how layout decisions impact wafer-level yield and performance consistency. Code-Based Layout Mastery: Advanced proficiency in Python and experience with functional layout frameworks. Version Control Expertise: Expert mastery of Git. DFT Mindset: Demonstrated experience in placing and routing test structures for automated wafer-scale probing. Verification Tools: Expert-level debugging of DRC in the EDA ecosystem, with the ability to translate foundry rule decks into layout code constraints. Education: M.S. in Electrical Engineering, Physics, or Computer Science with a focus on Physical Design. Deep familiarity using AI tools (e.g., LLMs, copilots) to accelerate engineering workflows, debugging, and problem-solving. Preferred Skills MEMS Layout: Experience designing layout functions for MEMS structures. Data-Driven Feedback: Ability to parse large-scale foundry PCM data to refine the function library parameters. Equal Opportunity Employer All qualified applicants will receive consideration for employment without regard to race, color, religion, age, sex, sexual orientation, gender identity, national origin, disability, protected veteran status, or any other characteristic protected by law. We may use artificial intelligence (AI) tools to support parts of the hiring process, such as reviewing applications, analyzing resumes, or assessing responses. These tools assist our recruitment team but do not replace human judgment. Final hiring decisions are ultimately made by humans. If you would like more information about how your data is processed, please contact us. Starting salary and title will depend on, and be commensurate with, relevant experience, skills, training, education, market demands, and the ultimate job duties and requirements. #J-18808-Ljbffr nEye.ai