Staff Physical Design Engineer ($300-400k pkg) (San Jose)

Staff ASIC Engineer (Physical Design OR STA)Total package up to $400k (Base up to $200k + bonus + stock)Total first year realistic income $350-400kLocations: San Jose, CA, Irvine, CA or Fort Collins, COIntroductionAre you an experienced ASIC engineer with strong expertise in physical design or STA, and a passion for working on bleeding-edge AI and high-performance silicon? Do you enjoy diving into complex EDA reports, identifying issues early, and collaborating with top-tier engineering teams to deliver next-generation chips?If you're excited about contributing to advanced AI/ML accelerators and infrastructure silicon, this role offers the opportunity to work at the forefront of semiconductor innovation.Top Reasons to Work With UsSupport customers building next-generation AI/ML, HPC, and infrastructure ASICsWork on cutting-edge silicon for AI workloads, including large-scale compute and accelerator architecturesCollaborate with highly experienced cross-functional engineering teamsGain exposure to advanced nodes, chiplet architectures, and high-performance design methodologiesContribute to customer program success from early engagement through productionBe part of a collaborative, technically strong environmentThe Role / ResponsibilitiesAs a Staff ASIC Engineer, you will work closely with senior engineers and internal teams to support customer ASIC programs focused on advanced AI and compute silicon. This is a primarily hands-on role, with opportunities to grow into broader technical ownership over time.Your responsibilities will include:Assisting in the execution of customer AI/ML ASIC programs across design, test, packaging, fabrication, bring-up, and productionSupporting customer teams with EDA tools, design flows, and methodology best practices for high-performance siliconHelping identify risks in quality, schedule, or dependencies and contributing to mitigation effortsRunning physical design or STA validation flows to ensure designs meet stringent tape-out standards for advanced nodesCollaborating with cross-functional teams to resolve complex implementation challenges in AI and compute architecturesStaying current with emerging AI silicon trends, IP, and implementation methodologiesSupporting program communication across engineering and internal partner teamsEssential SkillsExperience with multiple ASIC tape-outs (advanced nodes preferred)Strong understanding of PPA tradeoffs, especially in high-performance designsKnowledge of low power design and power management in compute-intensive systemsHands-on experience in physical design or STA, including relevant EDA tools and flowsExposure to broader ASIC flows (logic simulation, test, packaging)Scripting experience (TCL, shell, or similar)Strong communication and collaboration skillsBonus Points ForExperience with AI/ML accelerators, HPC, or large-scale compute SoCsExposure to SERDES or high-speed interfacesExperience in RTL design, microarchitecture, or front-end flowsKnowledge of DFT (scan, MBIST, repair)BenefitsHealth, dental, and vision insuranceLife and disability insurance FSA and HSA401k with matchESPPGenerous PTOAnnual bonus from 15-30% (depending on your level)VERY generous stocks!