RTL Design Engineer (San Jose)

WHAT YOU DO AT AMD CHANGES EVERYTHING At AMD, our mission is to build great products that accelerate next-generation computing experiences—from AI and data centers, to PCs, gaming and embedded systems. Grounded in a culture of innovation and collaboration, we believe real progress comes from bold ideas, human ingenuity and a shared passion to create something extraordinary. When you join AMD, you’ll discover the real differentiator is our culture. We push the limits of innovation to solve the world’s most important challenges—striving for execution excellence, while being direct, humble, collaborative, and inclusive of diverse perspectives. Join us as we shape the future of AI and beyond. Together, we advance your career. THE ROLE:We are looking for an adaptive, self-motivated design engineer to be part of a leading team to drive and improve AMD's abilities to deliver the highest quality, industry-leading technologies to market. As a key contributor, you will focus on RTL design and validation of high-speed interfaces such as Chip-to-Chip interconnect and highly configurable mufti-protocol PHYs. The design engineering team furthers and encourages continuous technical innovation to showcase successes as well as facilitate continuous career development. THE PERSON:You have a passion for digital design, and verification. You are a team player, have strong analytical and problem-solving skills and are willing to learn and ready to take on problems. KEY RESPONSIBILITIES:Perform RTL design of digital components.Work with functional verification team to meet coverage and quality standards.Analyze/fix Lint and CDC errors of the components.Guarantee quality/timely deliverables meeting project’s schedule.Help to improve/automate design process.Support post-silicon product bring-up/debug.PREFERRED EXPERIENCE:Working experience in designing digital components for high performance, low power FPGA/SOC.Combined Experience or relevant course work in some of the following areas:SerDes/Memory/Chip-to-Chip interconnect PHY DesignsDesign of digital circuits and components using Verilog/System VerilogDebugging in digital and mixed-signal simulation environment.Power-optimization of digital designs. Multi-clock domain designs.Design constraints for synthesis and static timing analysis.Logic synthesis, timing closure, logical equivalence checking.Scripting languages such as Perl, Tcl, or Python. Use of AI for productivity enhancementExcellent verbal and interpersonal communication skillsACADEMIC CREDENTIALS:Bachelors or Masters degree in Computer engineering/Electrical Engineering LOCATION: San Jose, CAThis role is not eligible for visa sponsorship.#LI-TB2#LI-HYBRID Benefits offered are described: AMD benefits at a glance.AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law. We encourage applications from all qualified candidates and will accommodate applicants’ needs under the respective laws throughout all stages of the recruitment and selection process.AMD may use Artificial Intelligence to help screen, assess or select applicants for this position. AMD’s “Responsible AI Policy” is available here.This posting is for an existing vacancy.