DDR PHY SI/PI Engineer — Channel & PDN Architect
Saicon
Saicon is seeking an experienced signal integrity and power integrity engineer to join the CT Server DDR team in Santa Clara, CA. You will define channel and PDN architectures, model SI/PI at the system level, and drive post-silicon validation with cross-functional teams. You will collaborate with design, package, board and firmware teams to meet SI/PI targets, debug issues across silicon, package and board, and translate requirements into robust PDN and channel implementations. #J-18808-Ljbffr Saicon
Vacancy posted 2 days ago
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