Senior ASIC RTL Engineer

Join Cisco's Silicon One team, where innovative hardware platforms are developed to power the AI era. As a key member of our development organization, you will collaborate with cross-functional teams to drive high-quality Design for Test (DFT) RTL, ensuring robust silicon solutions that meet Cisco’s performance standards.

Responsibilities:

• Collaborate with Front-end RTL and backend physical design teams to understand chip architecture.
• Drive high-quality Design for Test (DFT) RTL for silicon solutions.
• Ensure silicon solutions meet Cisco’s standards for performance and innovation.
• Participate in cross-functional teamwork to deliver advanced networking silicon.

Qualifications:

• Bachelor's or Master's Degree in Electrical or Computer Engineering.
• At least 7 years of experience in relevant fields.

Skills:

• Proficiency in Verilog/System Verilog coding.
• Experience with front-end tools (Verilog simulators, linting, CDC checkers, synthesis, formal verification).
• Familiarity with industry standard interface protocols (AMBA, JTAG, memories).
• Knowledge of power optimization techniques and power intent (UPF).
• Experience with DFT/MBIST and post-silicon debug is a plus.