Senior Implementation Methodology Engineer (Santa Clara)

NVIDIA has been transforming computer graphics, PC gaming, and accelerated computing for more than 25 years. It’s a unique legacy of innovation that’s fueled by great technology—and amazing people. Today, we’re tapping into the unlimited potential of AI to define the next era of computing. An era in which our GPU acts as the brains of computers, robots, and self-driving cars that can understand the world. Doing what’s never been done before takes vision, innovation, and the world’s best talent. As an NVIDIAN, you’ll be immersed in a diverse, supportive environment where everyone is inspired to do their best work. Come join the team and see how you can make a lasting impact on the world.We want a skilled and motivated Implementation Methodology Engineer for NVIDIA's elite VLSI team. This role involves owning synthesis methodology development in the RTL2GDS pipeline and supporting advanced-node chip development. You will lead aggressive PPA optimization campaigns and invent next-generation efficiency automation that multiplies engineering throughput across build teams. Your work will be realized in the world’s most advanced CPU silicon! If you are a hands-on technical leader who thrives at the intersection of physical design methodology, data-driven optimization, and scalable automation, this role offers an outstanding chance to create lasting impact in silicon engineering.What You'll Be Doing:Own and continuously improve the end-to-end RTL2GDS implementation methodology — covering synthesis, place & route, CTS, and equivalence checking — for advanced-node CPU builds.Evaluate new EDA tools and process node capabilities. Deliver clear adoption recommendations. Serve as the technical liaison between internal teams and EDA vendors (Synopsys, Cadence) to resolve tool issues and influence vendor roadmaps.Define and enforce implementation methodology BKMs and flow standards across development teams; maintain user documentation and lead training on tools and flows.Build and complete rigorous A/B and multi-variant experiments to quantitatively compare flows, engine settings, and optimization strategies for QoR impact.Drive aggressive PPA targets throughout the full implementation cycle. Conduct deep root-cause analysis on timing closure bottlenecks, power limiters, and long-tail QoR issues. Develop methodologies to resolve these problems at scale.Architect and build Python/TCL/Perl automation frameworks that reduce manual engineering effort and improve design turnaround time across implementation teams.Identify systemic efficiency bottlenecks across the implementation flow and eliminate them through targeted automation, data-driven regression infrastructure, and AI/ML-assisted flow optimization.Partner with architecture, RTL, DFT, physical build, and sign-off teams to surface PPA opportunities early and translate methodology improvements into measurable silicon impact.What We Need to See:BS or MS in Electrical Engineering, Computer Engineering, Computer Science, or a related field, or equivalent experience.6+ years of hands-on proven experience in ASIC implementation methodology and EDA tool/flow development.Deep, practical expertise in the complete RTL2GDS flow: synthesis, DFT, floorplanning, placement, CTS, routing, and MCMM STA.EDA Tool Proficiency: Power user of synthesis and place-and-route tools from Synopsys (DC/FC, ICC2, PrimeTime) and/or Cadence (Genus, Innovus, Tempus).Prior experience in data-focused EDA tool evaluation, flow benchmarking, and methodology development with demonstrated PPA impact.Strong scripting proficiency in Python, TCL, Perl, and/or Make for flow automation and analysis.Demonstrated ability to drive complex, cross-functional technical initiatives — aligning build, CAD, and EDA vendor teams toward shared goals.Excellent problem-solving, debugging, and analytical skills with a track record of simplifying complex, cluttered environments.Strong interpersonal and communication skills; able to translate technical findings into actionable recommendations for diverse audiences.Ways to Stand Out from the Crowd:Demonstrated application of AI/ML or GenAI techniques to physical build, QoR analysis, flow automation, or design space exploration — in production or research contexts.Solid understanding of front-end flows and methodology: RTL build intent, DFT insertion, synthesis constraints, and UPF/CPF low-power build — enabling an end-to-end perspective.Widely considered to be one of the technology world’s most desirable employers, NVIDIA offers highly competitive salaries and a comprehensive benefits package. As you plan your future, see what we can offer to you and your family Your base salary will be determined based on your location, experience, and the pay of employees in similar positions. The base salary range is 168,000 USD - 264,500 USD.You will also be eligible for equity and benefits.Applications for this job will be accepted at least until June 16, 2026.This posting is for an existing vacancy. NVIDIA uses AI tools in its recruiting processes.NVIDIA is committed to fostering an inclusive work environment and proud to be an equal opportunity employer. As we highly value diversity in our current and future employees, we do not discriminate (including in our hiring and promotion practices) on the basis of race, religion, color, national origin, gender, gender expression, sexual orientation, age, marital status, veteran status, disability status or any other characteristic protected by law.SummaryLocation: US, CA, Santa ClaraType: Full time