Chip Lead & Physical Design Director — Drive SoC PPA
Cadence Design Systems Inc
Cadence Design Systems in Austin, TX is seeking a highly experienced Physical Design Architect/Chip Lead to drive RTL-to-GDS efforts for SoCs in data centers, automotive, and AI domains. You will lead a PD team, influence sign-off criteria, and collaborate with customers to meet PPAS targets. 15+ years in PD with extensive EDA tool experience, especially Genus, Innovus, and PrimeTime, are expected. #J-18808-Ljbffr Cadence Design Systems
Vacancy posted 3 days ago
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