Staff Analog Design Engineer

At d-Matrix, we are focused on unleashing the potential of generative AI to power the transformation of technology. We are at the forefront of software and hardware innovation, pushing the boundaries of what is possible. Our culture is one of respect and collaboration.We value humility and believe in direct communication. Our team is inclusive, and our differing perspectives allow for better solutions. We are seeking individuals passionate about tackling challenges and are driven by execution. Ready to come find your playground? Together, we can help shape the endless possibilities of AI. Role Overviewd-Matrix is looking for a Staff Analog Design Engineer to lead analog-mixed signal IC design for our next-generation AI inference accelerators. This role owns circuit design for two critical subsystems: our in-memory-compute engine and the die-to-die serial interface that enables scale-out. You will drive design from schematic through silicon bring-up, guiding layout engineers working in deep sub-micron process nodes (7nm and below) and ensuring designs meet low-power performance targets across process-voltage-temperature corners. You will partner closely with layout engineers, backend/digital integration teams, and cross-site colleagues to deliver silicon-ready designs. This is a high-impact role for someone who wants to shape the analog foundations of state-of-the-art AI hardware.What You Will DoDesign analog-mixed signal circuits using industry-standard tools such as Cadence and SynopsysDevelop schematic-level circuit designs and conduct system-level performance analysisBuild test benches to support simulation and verification, including Monte Carlo yield analysis across PVT cornersGuide layout engineers on circuit layout in deep sub-micron process nodes (7nm and below), including hands-on minor layout adjustments as neededPartner with backend engineers to integrate design and layout, and provide circuit models to support backend verificationSupport testboard design for silicon bring-up, bench debug, and characterizationBuild scripts to support silicon bring-up and test feature validationWhat You Will BringBS, MS, or PhD in Electrical Engineering with 5+ years of related professional experience in high-speed circuit design (e.g., phase interpolators, clocking, PLL design)Experience with schematic capture, SPICE simulation, and Monte Carlo simulationExperience with circuit layout, extraction, and back-annotated simulationExperience with channel modeling using MATLAB or similar toolsStrong cross-functional communication and collaboration skills, with the ability to work effectively across distributed, cross-site teamsStrong analytical and problem-solving skills, with the ability to manage multiple priorities in a fast-paced environmentPreferred QualificationsWe'd be excited about candidates with deep expertise in any one of the following areas:SerDes verification & characterization — building/maintaining analog verification infrastructure (testbenches, regressions, Monte Carlo campaigns), migrating blocks across process nodes, or reliability analysis (EM, IR drop, ESD/latch-up)Clocking & CDR — ownership of a low-jitter PLL, phase interpolator, or CDR loop through silicon at 25 Gbps+ per lane, including bang-bang/baud-rate/DSP-assisted CDR architecturesTX/RX datapath — high-speed driver or receive front-end design (CTLE, VGA, samplers), DFE/FFE equalization, or PAM4/DSP-based receiver architecturesDie-to-die interconnect experience (UCIe, BoW, or proprietary D2D PHY), familiarity with relevant specs (OIF CEI-112G/224G, IEEE 802.3, PCIe Gen6/7), or standards body participationEqual Opportunity Employment Policyd-Matrix is proud to be an equal opportunity workplace and affirmative action employer. We’re committed to fostering an inclusive environment where everyone feels welcomed and empowered to do their best work. We hire the best talent for our teams, regardless of race, religion, color, age, disability, sex, gender identity, sexual orientation, ancestry, genetic information, marital status, national origin, political affiliation, or veteran status. Our focus is on hiring teammates with humble expertise, kindness, dedication and a willingness to embrace challenges and learn together every day.d-Matrix does not accept resumes or candidate submissions from external agencies. We appreciate the interest and effort of recruitment firms, but we kindly request that individual interested in opportunities with d-Matrix apply directly through our official channels. This approach allows us to streamline our hiring processes and maintain a consistent and fair evaluation of al applicants. Thank you for your understanding and cooperation. Compensation Range: $155K - $250KLocationSanta ClaraEmployment TypeFull timeLocation TypeHybridDepartmentHardware EngineeringCompensation$155K – $250K • Offers Equity • Offers BonusThe pay range below is for all roles at this level across all US locations and functions. Individual pay rates depend on a number of factors—including the role’s function and location, as well as the individual’s knowledge, skills, experience, education, and training. We also offer incentive opportunities that reward employees based on individual and company performance. This is in addition to our diverse package of benefits centered around the wellbeing of our employees and their loved ones. In addition to the usual Medical/Dental/Vision/401k, our inclusive rewards plan empowers our people to care for their whole selves. An investment in your future is an investment in ours.