Senior Principal SI/PI Engineer - High-Speed IP Debug
Cadence Design Systems
Cadence Design Systems is seeking a Sr Principal SI/PI Engineer to join the HPP IP R&D Group. This hands-on role focuses on high-speed IP products, SI/PI optimization, and collaboration with chip designers. You will work on test chip package design, evaluation board optimization, and provide channel models. Requires MS/PhD in EE, 3+ years SerDes/PHY experience, and proficiency with Sigrity/HFSS/SIwave; IBIS-AMI simulations; lab instrumentation.
#J-18808-LjbffrVacancy posted 5 days ago
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