PCIe Verification Engineer

PCIe Verification Engineer Location: San Jose, CA Or Silver Lake, CO (Day One Onsite) Position Type: Contract Job Description: Experience: 7+ Years Education: Bachelor/Master of Engineering (B.E./B.Tech/MS) in Electronics, Electrical, Computer Engineering, or a related field Role Summary: Drive the pre-silicon verification of next-generation PCIe Switch and Retimer designs across Gen4, Gen5, and Gen6 specifications. Utilizing SystemVerilog and UVM, you will ensure robust protocol compliance, high-performance throughput, and seamless interoperability for cutting-edge silicon. Key Responsibilities: Strategic Planning: Architect and execute comprehensive PCIe verification plans to ensure full specification coverage. Environment Development: Build and maintain sophisticated, UVM-based verification environments from the ground up. Protocol Deep-Dive: Verify intricate PCIe protocol behaviors, including LTSSM transitions, link training flows, and complex error handling mechanisms. Feature Validation: Validate specialized Switch and Retimer features alongside cross-vendor interoperability. RTL Debugging: Perform rigorous debug of RTL and protocol-level issues while conducting detailed functional and code coverage analysis. Required Skills: Protocol Expertise: Strong command of PCIe protocols, specifically Gen4 and Gen5, with Gen6 knowledge considered a significant advantage. Methodology: Advanced proficiency in SystemVerilog, UVM, and the implementation of functional assertions. Tooling: Extensive experience navigating industry-standard simulators such as VCS, Questa, or Xcelium. Nice to Have: Compliance & Physical Layer: Familiarity with PCI‑SIG compliance testing, SerDes/Signal Integrity fundamentals, and hardware emulation environments. #J-18808-Ljbffr Highbrow LLC