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  •  ...A leading tech company is seeking an ASIC Design Verification Engineer I in San Francisco, CA. You will work collaboratively with a talented...  ...hardware description languages and RTL design tools. This is an entry-level, full-time position offering a chance to impact billions... 
    Entry level
    Full time

    Cisco

    San Francisco, CA
    4 days ago
  •  ...ASIC Design Verification Engineer I (Full Time) United States Please note this posting is to advertise...  ...and networking and take it to a new level in any one of the following product...  ...periods of time. Seniority Level Entry level Employment Type Fulltime... 
    Entry level
    Full time

    Cisco

    San Francisco, CA
    4 days ago
  • $76.5k - $103.5k

     ...ASIC and/or FPGA Design and Verification Engineers (Entry Level, Associate, or Experienced) Company: The Boeing Company Boeing Space, Intelligence & Weapons Systems has an exciting opportunity for multiple ASIC and/or FPGA Design and Verification Engineers (Entry... 
    Entry level
    Permanent employment
    Full time
    Work experience placement
    Interim role
    Relocation
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    Work visa
    Flexible hours
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    Boeing

    Mountain View, CA
    1 day ago
  •  ...solutions for the consulting, architecture, engineering, project controls, procurement,...  ...Execution of C/Q/V protocols. Walkdown and verification of system drawings (P&IDs, as-builts,...  ...work experience. ~ This is an entry-level position. ~ Experience in Pharmaceutical... 
    Entry level
    Work experience placement
    Work at office
    Night shift

    IPS-Integrated Project Services

    Indianapolis, IN
    9 days ago
  •  ...Execution of C/Q/V protocols. Walkdown and verification of system drawings (P&IDs, as-builts,...  ...degree in related field preferred. Entry level position. 0 to 2 years of relevant...  ...technical consulting, architecture, engineering, procurement, construction management,... 
    Entry level
    Work experience placement
    Work at office
    Night shift

    IPS-Integrated Project Services

    Indianapolis, IN
    9 days ago
  • $143.3k

     ...are seeking experienced Hardware Design Engineers to work with partners and vendor and build...  ...job responsibilities - Develop formal verification plans, implement and verify state-of-the...  ...members. We have a broad mix of experience levels and tenures, and we’re building an... 
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    Local area
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    Annapurna Labs Inc.

    Cupertino, CA
    9 hours agonew
  •  ...Access preferred. In process of obtaining an undergraduate engineering degree. Ability to interpret blueprints required....  ...approval process. Requirements: BSME Degree preferred Entry level Engineer – preferred with intern experience, particularly in... 
    Entry level
    Internship

    US Tsubaki Automotive, LLC

    Portland, TN
    4 days ago
  • $181.1k - $318.4k

    A leading technology company in San Francisco seeks a PHY Design Verification Engineer to join its wireless silicon development team. The role involves pre-silicon RTL verification of wireless PHY and its interfaces, requiring advanced knowledge in Verilog and SystemVerilog... 
    Suggested
    Full time

    Apple Inc.

    San Francisco, CA
    16 days ago
  •  ...A leading technology company is seeking an ASIC Design Verification Engineer to optimize low latency SoCs for critical applications. The ideal candidate will have extensive experience in design verification, UVM, and a strong background in programming. In this role, you... 
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    Full time

    SQL Pager LLC

    San Francisco, CA
    16 days ago
  • $129.8k

     ...countries around the world. We are seeking an experienced Design Verification Engineers to build the next generation of our cloud server platforms....  ...supporting new members. We have a broad mix of experience levels and tenures, and we’re building an environment that... 
    Suggested
    Local area
    Work from home

    Annapurna Labs Inc.

    Cupertino, CA
    9 hours agonew
  •  ...Systems Test & Verification Engineer -- Hybrid - Burlington, VT Were looking for a Systems Test and Verification Engineer with strong experience...  .... What youll do: Develop and execute system-level test and verification activities Create, maintain, and review... 
    Suggested
    Part time

    Clear Point Consultants

    Burlington, VT
    1 day ago
  •  ...below: Architect block and full-chip verification environments using HVLs and constrained...  ...specifications and write block and chip-level tests in C,SV,UVM ○ Debug RTL and Gate simulations and work with design engineers to verify fixes. ○ Write diagnostics... 
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    Mirafra Technologies

    San Jose, CA
    4 days ago
  •  ...Manufacturing Facility is looking for a Process Performance Verification Leader II (Engineering) to join our Final Assembly Line based in ** Mobile, AL.*...  ...visiting the shop floor. * Take your career to a new level and apply online now! * This job requires an awareness of... 
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    Airbus Americas, Inc.

    Mobile, AL
    3 days ago
  •  ...Job Description Junior Recruiter (Entry-Level | Bilingual English/Spanish) Spring, TX | Mon–Fri | 7:30 AM–4:30 PM Looking to break into recruiting? We're hiring a people-oriented , self-motivated Junior Recruiter to join our team in a developmental role... 
    Entry level

    NESC Staffing

    Spring, Montgomery County, TX
    5 days ago
  • $85k

     ...a robust wellness program paid time off for vacation, holidays, and sick days and much more.   ***This Engineering role can be filled at the Entry, Mid-level or Senior Engineer level. Please see minimum qualifications list below for each level***   Entry-Level -... 
    Entry level

    Constellation Energy

    Joliet, IL
    17 days ago
  •  ...OpenAIs Hardware organization develops silicon and system-level solutions designed for the unique demands of advanced AI workloads...  ...of frontier AI models. Were looking for experienced Design Verification (DV) Engineers to ensure functional correctness and robust design for our... 
    Full time

    OpenAI

    San Francisco, CA
    16 days ago
  • $181.1k - $318.4k

     ...transform the user experience at the product level, all of which is driven by a world-class vertically integrated engineering team spanning RF/Analog architecture and...  ...design, VLSI/RTL design and integration, Design Verification, Emulation, Test and Validation, and FW/SW... 
    Full time
    Relocation

    Apple Inc.

    San Francisco, CA
    16 days ago
  •  ...As a Design Verification (DV) Engineer, you will be part of an advanced architecture team that is exploring new hardware designs to improve our...  ...overall debug skills ~ Experience verifying at multiple levels of logic from IP to SoC ~ Experience with industry standard... 
    Full time

    Amazon

    San Francisco, CA
    2 days ago
  •  ...Job Title: Verification Engineer (SystemVerilog/UVM)&##128205; Location: Sunnyvale, CA or Austin, TX ~514 years experience Responsibilities...  ...-based verification environments for IP, subsystem, and SoC-level testing. Understand design specifications and create... 
    Part time

    Globex Digital

    San Diego, CA
    1 day ago
  • $32 per hour

     ...Job Description Title: Manufacturing Engineer Location: West Columbia, SC Hire Type: Contract to Hire Shift: 1st Shift...  ...experience/training required. Experience requirements vary by level (entry to senior): Entry Level: 0–3 years Mid Level: 3–8 years... 
    Entry level
    Contract work
    Work at office
    Shift work
    Day shift

    Sterling Engineering

    West Columbia, SC
    9 days ago
  •  ...have an opportunity for an outstandingly hardworking design verification engineer! As a member of our wide-ranging group, you will have the rare...  ...failures. You will also learn to develop block, IP and SoC level testbenches track and report DV progress using a variety of... 
    Full time
    Work experience placement

    Apple Inc.

    San Francisco, CA
    16 days ago
  • $190k - $265k

     ...Join to apply for the Design Verification Engineer role at Eridu AI Join to apply for the Design Verification Engineer role at Eridu AI...  ...models. Todays AI performance is frequently limited by system-level bottlenecks. Eridu AI delivers multiple industry-first... 
    Full time

    Eridu AI

    San Francisco, CA
    16 days ago
  •  ...ASIC Design Verification Engineer Client Overview Our client is building the first latency optimized SoC for their industry. Using its proven...  .... Job Responsibilities Architect and build an SoC-level and unit-level UVM verification environment. Collaborate... 
    Full time
    Night shift

    SQL Pager LLC

    Sunnyvale, CA
    16 days ago
  •  ...Job Title: Design Verification Lead Engineer Location: Redmond, Seattle, Washington Exp: 8-15 yrs He should have some lead experience...  ...expertise in System Verilog /UVM for Unit/Module level Verification Should have Lead Design Verification Team (... 
    Part time

    CoreTek Labs

    Redmond, WA
    1 day ago
  •  ...A leading technology company in San Francisco is seeking a highly skilled design verification engineer to ensure bug-free first silicon for new products. The role involves developing methodologies for verification, creating test plans, and utilizing advanced tools and... 
    Full time

    Apple Inc.

    San Francisco, CA
    16 days ago
  •  ...Title Design Verification Engineer Internal IP Location Bay Area (hybrid) or Toronto About the Company A fast-growing AI startup designing next-generation compute hardware. The company specializes in building high-performance IP blocks and accelerators... 
    Full time

    Amadeus Search

    San Francisco, CA
    5 days ago
  •  ...One of our leading client is looking for Design Verification Engineer in Sunnyvale CA Key Responsibilities: Strong understanding of SV...  ...Verilog-based verification environments for IP/subsystem/SoC level testing Develop directed and random testcases , perform... 
    Part time

    Programmers.io

    Sunnyvale, CA
    1 day ago
  • $195k - $265k

     ...Key Responsibilities Specialized Verification Strategy: Develop verification infrastructure...  ...the team to execute comprehensive gate-level simulations, including timing and power...  ...suite. Offer actionable feedback to design engineers, focusing on identifying gaps and... 
    Full time

    Eridu

    San Francisco, CA
    11 days ago
  • $140k - $225k

     ...Tara Technical Solutions Recruiting for a Principal ASIC Verification Engineer role. Principal ASIC Verification Engineer San Jose Fulltime...  ...work experience. ~ Experience verifying designs at system level and block level. ~ Fluent knowledge of RTL verification... 
    Full time
    Work experience placement

    Tara Technical Solutions (TTS)

    San Francisco, CA
    3 days ago
  •  ...A leading tech company in San Francisco seeks a Design Verification Engineer to develop verification methodologies and plans, ensuring the functionality of complex hardware designs. You will work closely with various engineering teams and require a strong background in... 
    Full time

    Amazon

    San Francisco, CA
    2 days ago