Semiconductor Device Modeling Engineer

Overview Intel is shaping the future of technology to help create a better future for the world. Our work in AI, analytics, and cloud-to-edge technology drives innovations. A career at Intel offers opportunities to power breakthroughs and improve everyday life. Learn more about Life at Intel. About the team and organization Compact Device Modeling Group (CDMG) is part of Intel's Design Technology Platform (DTP). DTP enables Intel to deliver design, development and manufacturing services that help Intel Foundry customers bring products to market. As a member of CDMG, you will help co-optimize Intel\'s state-of-the-art process technology to enable best-in-class products for data-centric applications. As a semiconductor device modeling engineer, you will play a key role in supporting compact modeling activities for Intel\'s new technologies. Responsibilities The role involves supporting compact modeling activities for Intel\'s new technologies and collaborating with cross-functional teams to drive design enablement and product performance. Minimum Qualifications Bachelor\'s degree in Electrical Engineering or a related discipline and 5+ years of experience; or Master\'s degree with at least 3 years of industry experience in the semiconductor field; or Ph.D. in Electrical Engineering or a related discipline. Graduate coursework or research experience in semiconductor device physics or 5+ years of work experience in semiconductor device physics. 1+ years of Python scripting for data analysis, automation and documentation. Preferred Qualifications Ph.D. in Electrical Engineering or a related discipline with 3+ years of industry experience in the semiconductor field. Proficiency with extraction tools (e.g., ICCAP, MBP) and commercial simulators (e.g., HSPICE, Spectre). Hands-on experience with BSIM-CMG and other compact models for transistor modeling at advanced nodes (e.g., FinFET, GAA) including experience in one or more of the following areas: Experience developing Layout-dependent effects (LDE) for FinFET or GAAFET technologies and their impact on circuit performance. Development of methodologies for device targeting and benchmarking circuits (e.g., ring oscillators), including corners and statistical variation models. Modeling using Open Model Interface (OMI). Strong understanding of process flow, layout, and basic circuit design/simulation. Modeling self-heating effects and their influence on device and circuit performance. Proven ability to collaborate across multiple teams and geographies. Experience with machine learning algorithms and their application in data analysis and compact model development. Benefits Intel offers a total rewards package that includes competitive pay, stock bonuses, and benefits such as health, retirement, and vacation. Details of benefits are available through Intel Benefits. Additional information Annual salary range for jobs in the US: $149,600.00 - 284,580.00 USD. The range reflects the minimum and maximum target compensation across all US locations. Individual pay is determined by location and other factors. The recruiter can share specifics for your location during the hiring process. Work Model for this Role This role will require an on-site presence. Job posting details (work model, location, time type) are subject to change. EOE and Compliance Intel is an equal opportunity employer. Intel is committed to Responsible Business Alliance (RBA) compliance and ethical hiring practices. We do not charge any fees during the hiring process. If you are asked to pay any fees, report it to your recruiter. #J-18808-Ljbffr Intel Corporation