ASIC Power Engineer, ML Accelerators

Join Google's AI and Infrastructure team as an ASIC Design Engineer, focusing on the development of cutting-edge TPU technology that powers AI/ML applications. This role involves enhancing power efficiency in silicon design, contributing to innovative solutions that impact millions of users worldwide. Responsibilities: Contribute to design power modeling and drive convergence to power goals. Investigate, specify, and deploy architectural and microarchitectural power optimization techniques. Define best practices and methodologies to achieve low-power designs. Collaborate with cross-functional software and system teams to create novel power management architectures to meet power goals. Qualifications: Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field, or equivalent practical experience. 8 years of experience in silicon design or architecture, including logic design, power architecture, performance, or SoC design. Experience with power design, power modeling, power architecture, or power reduction methodologies. Skills: Master's degree or PhD in Electrical Engineering, Computer Engineering, or Computer Science, with an emphasis on computer architecture (preferred). Experience defining and implementing chip-wide power management architectures and designs. Understanding of modern power and thermal management techniques, including DVFS and system-level tradeoffs. Ability to solve open-ended power and performance problems under ambiguity. #J-18808-Ljbffr Anysilicon