Memory Layout Engineer - Lower-Node SRAM Expert
leadIC Design Pvt Ltd
leadIC Design Pvt Ltd is seeking a Memory Layout Engineer with 5–7 years of hands-on experience in memory layout design, mainly on lower technology nodes. The successful candidate will perform layout development, verification, and work closely with design and verification teams. This role demands expertise in memory layout for SRAM/memory blocks and experience with DRC/LVS closure to ensure compliance with density requirements. #J-18808-Ljbffr leadIC Design Pvt Ltd
Vacancy posted 4 days ago
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