Senior Staff Collateral Design and DFM Engineer (Santa Clara)

Job Details:Job Description: Shape the Future of Semiconductor Innovation at Intel FoundryOrganization Overview: Manufacturing Development Customer Engineering (MDCE) is Intel's newest organization within Intel Foundry Technology Manufacturing (FTM). We bridge the critical gap between Technology Development (TD) and High-Volume Manufacturing (HVM), advancing technology nodes from initial product qualification to high-yield production across multiple products while enhancing technologies for our foundry customers.Intel's Chandler, Arizona facility is constructing state-of-the-art fabrication facilities for cutting-edge technology nodes, including Intel 18A and beyond. Additionally, we're developing legacy technologies with foundry partners to launch HVM operations serving global foundry customers.Position Summary: We seek an experienced Senior Staff Collateral Design and DFM Engineer to join our MDCE team and help build a world-class Foundry Customer Engineering organization. In this role, you will be at the forefront of high-volume manufacturing (HVM) and ramp leading-edge advanced logic technologies. You will play a pivotal role in inventing and enhancing Design for Manufacturability (DFM) methodologies that drive measurable improvements in performance, yield, and ramp speed across a broad and dynamic product portfolio.Key ResponsibilitiesLead cross-functional teams spanning Process Integration, Device, Yield, Design, OPC/RET, Design Rules, DTP, and CAD to define and continuously enhance DFM rules that accelerate yield improvement and technology ramp on advanced logic nodesTranslate silicon learning and yield insights into actionable feedback for design teams, enabling timely updates to layout and DTCO methodologies and flows that catch yield issues earlier in the design cycleDevelop, refine, and optimize yield tools and flows within the foundry environment, supporting inline yield detection and continuous process optimizationDefine and evolve DFM methodologies by deeply understanding silicon process flows, predicting layout and design marginalities, and collaborating with cross-functional partners to develop robust mitigation rulesDrive scribe line layout design and process monitoring structure development to support advanced node characterization and manufacturing readinessManage design rule development, validation, and waiver processes, ensuring alignment between manufacturing constraints and customer design requirementsServe as the key interface between Process Integration, Yield, Device, and Design teams acting as a trusted technical bridge across all stakeholdersSupport foundry customers across multiple market segments by developing and implementing tailored DFM solutions that meet diverse application requirementsCore CompetenciesExcellent communication and collaboration skills, with demonstrated ability to engage effectively with design teams, process engineers, and external customers across industry segmentsAbility to manage multiple concurrent projects and prioritize effectively in a fast-paced environmentQualifications:The Minimum qualifications are required to be initially considered for this position. Minimum qualifications listed below would be obtained through a combination of industry relevant job experience, internship experience and / or schoolwork/classes/research. The preferred qualifications are in addition to the minimum requirements and are considered a plus factor in identifying top candidates.Minimum Qualifications Master’s in Electrical Engineering, Physics, or a closely related field6+ years of experience in DTCO and/or DFM within a semiconductor foundry or advanced technology development environmentExperience in DTCO methodologies, including SRAM and Standard Cell designExperience leading cross-functional teams in defining derivative architectures encompassing design rules, transistors, and interconnectsHands-on experience in advanced node test chip design and scribe line optimization across 3nm–16nm FinFET or sub-3nm GAA FET technologies, including Backside Power Delivery (BSPD)Preferred QualificationsPh.D. in Electrical Engineering, Physics, or a closely related fieldExperience in scripting and coding for design automation and flow developmentExperience with physical design flows for yield analysis, DRC, and verification Experience in a foundry environment delivering DFM solutions for varied customer requirements across multiple market segmentsExperience with the foundry ecosystem, including customer design flows and manufacturing constraints across diverse application domainsWhy Join MDCE?At Intel's MDCE organization, you will work on some of the most advanced semiconductor technologies in the world, with the unique opportunity to shape how those technologies reach high-volume production. You will collaborate with world-class engineers, influence foundry strategy, and directly impact Intel's ability to serve the next generation of global customers.Job Type:Experienced HireShift:Shift 1 (United States of America)Primary Location: US, California, Santa ClaraAdditional Locations:US, Arizona, Phoenix, US, Oregon, HillsboroBusiness group:Intel Foundry strives to make every facet of semiconductor manufacturing state-of-the-art while delighting our customers -- from delivering cutting-edge silicon process and packaging technology leadership for the AI era, enabling our customers to design leadership products, global manufacturing scale and supply chain, through the continuous yield improvements to advanced packaging all the way to final test and assembly. We ensure our foundry customers' products receive our utmost focus in terms of service, technology enablement and capacity commitments. Employees in the Foundry Technology Manufacturing are part of a worldwide factory network that designs, develops, manufactures, and assembly/test packages the compute devices to improve the lives of every person on Earth.Posting Statement:All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.Position of TrustN/ABenefitsWe offer a total compensation package that ranks among the best in the industry. It consists of competitive pay, stock bonuses, and benefit programs which include health, retirement, and vacation. Find out more about the benefits of working at Intel. Annual Salary Range for jobs which could be performed in the US: $161,550.00-317,600.00 USDThe range displayed on this job posting reflects the minimum and maximum target compensation for the position across all US locations. Within the range, individual pay is determined by work location and additional factors, including job-related skills, experience, and relevant education or training. Your recruiter can share more about the specific compensation range for your preferred location during the hiring process.Work Model for this RoleThis role will be eligible for our hybrid work model which allows employees to split their time between working on-site at their assigned Intel site and off-site. * Job posting details (such as work model, location or time type) are subject to change.*ADDITIONAL INFORMATION: Intel is committed to Responsible Business Alliance (RBA) compliance and ethical hiring practices. We do not charge any fees during our hiring process. Candidates should never be required to pay recruitment fees, medical examination fees, or any other charges as a condition of employment. If you are asked to pay any fees during our hiring process, please report this immediately to your recruiter.SummaryLocation: US, California, Santa Clara; US, Arizona, Phoenix; US, Oregon, HillsboroType: Full time