Validation Engineer

Pcie, Cxl And Highspeed Io Validation EngineerAt AMD, our mission is to build great products that accelerate next-generation computing experiences—from AI and data centers, to PCs, gaming and embedded systems. Grounded in a culture of innovation and collaboration, we believe real progress comes from bold ideas, human ingenuity and a shared passion to create something extraordinary. When you join AMD, you'll discover the real differentiator is our culture. We push the limits of innovation to solve the world's most important challenges—striving for execution excellence, while being direct, humble, collaborative, and inclusive of diverse perspectives. Join us as we shape the future of AI and beyond. Together, we advance your career.We are looking for a dynamic, energetic, and visionary principal validation engineer to join our growing datacenter CPU post silicon validation team, in particular in the areas of highspeed IO such as PCI Express and Compute Express Link (CXL), multi-socket and inter-die interfaces. As a key contributor to the success of AMD's product, you will be part of a leading team to drive and improve AMD's abilities to deliver the highest quality, industry leading technologies to market. The Systems Design Engineering and validation team fosters and encourages continuous technical innovation to showcase successes as well as facilitate continuous career development.Key Responsibilities:Develop and execute feature enablement and validation test plans for SoC- and system-level SoC features across all AMD Server products for High-Speed IODevelop test content for both focus testing as well as system level stress testing of IO domain plus cross product stress testingDevelop post-silicon validation infrastructure (software, hardware, automation environment, and lab setup)Test interactions between various SoC features using validation infrastructureDebug and drive root-cause analysis for SoC related issuesCollaborate with cross-functional teams in developing tools to improve SoC validation and debugWork with cross-functional teams to improve post-silicon validation test strategy, methodology, and processPreferred Experience:Proven hands on experience in soc design or validation of high speed IO interfacesHas experience in PCIe Gen5/6+, CXL, UCIe or proprietary inter-die and multi-socket server interface in either electrical or functional or both.Understanding of modern x86 microprocessor architecture and Server platform architecture is highly desiredExperience developing validation methodologies and infrastructureTest plan and workload development experienceParticipated in silicon bring up and debug, support to internal engineering teamsAble to execute and drive success of programs with multiple projects on the goDebug skills at both SoC and system levelFamiliarity with programming / scripting language (C/C++, Python, Perl,...)Working knowledge of Server OSes (Linux, Windows)Must be a self-starting team player with excellent communication skills who can work with minimal guidanceForward thinker that drives improvement to development process, code architecture and fosters a spirit of innovation and continuous improvementStrong verbal and written English communication skillsExtensive experience with common lab equipment, including protocol/logic analyzers, oscilloscopes, etc.Extensive experience with board/platform-level debug, including delivery, sequencing, analysis, and optimizationExtensive knowledge of system architecture, technical debug, and validation strategyStrong analytical/problem-solving skills and pronounced attention to detailsAcademic Credentials:BSEE/CSE/CS with 7+ years of experience orMSEE/CSE/CS with 5+ years of experienceLocation:Austin, TXSanta Clara, CASeattle, WAPhoenix, AZThis role is not eligible for visa sponsorship.