Semiconductor 3D Architecture, Director

Job Description

About Us

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Adeia Inc. (Nasdaq: ADEA) develops foundational innovations that shape how the world computes, connects and experiences entertainment. Its inventions span a broad range of semiconductor and media technologies, including 3D interconnect (hybrid bonding) and advanced thermal management for AI datacenters, as well as content discovery, personalization, and streaming. These inventions are licensed to leaders across the chip design and manufacturing, consumer electronics, automotive, digital entertainment, and e-commerce industries. Adeia’s innovations enable more powerful and efficient products, and more immersive, personalized experiences across billions of devices worldwide. Learn more at

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Position Summary

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The Semiconductor 3D Architecture, Director provides enterprise technical leadership in memory and logic integration, defining the long-term technology strategy for one of Adeia’s key semiconductor innovation areas. The role establishes and leads the company’s memory logic innovation program, identifying strategic technology investments, guiding cross-functional R&D, and translating emerging technologies into differentiated semiconductor platforms and high-value IP licensing opportunities. Working closely with the VP, Emerging Technology & Discovery, this leader shapes Adeia’s technical direction in memory logic architectures while building strategic partnerships across the semiconductor ecosystem. The role serves as the company’s recognized technical authority in memory logic integration, influencing engineering priorities, technology strategy, industry collaboration and future innovation platforms.

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Key Responsibilities

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Technology Strategy & Innovation

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• Own the Memory Logic Innovation Program. Establish and lead Adeia’s semiconductor strategy for memory logic integration, defining long-term technology roadmaps, innovation priorities, and strategic investment areas aligned with the company’s semiconductor strategy.
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• Build a New Semiconductor Technology Vertical. Identify, evaluate, and mature high-impact technologies into differentiated semiconductor platforms that expand Adeia’s technology portfolio and create future IP licensing opportunities.
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• Drive Technology Portfolio Decisions. Evaluate emerging technologies, competitive landscapes, and market opportunities and guide strategic technology decisions to prioritize innovation investments and industry collaborations.
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Architecture Leadership & Technology Development

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• Lead Computer Architecture Innovation. Direct the development of novel device, circuit, package, and system architectures that address complex memory logic challenges and create differentiated technical capabilities.
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• Drive Cross-Layer Technology Development. Lead architectural exploration across transistor physics, standard cell design, circuit implementation, physical layout, place and route, memory and logic subsystem design, and system architecture to identify breakthrough innovation opportunities.
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• Direct Technology Validation. Oversee modeling, simulation, prototype development, and technical validation activities to mature concepts into scalable technology platforms and future licensing opportunities.
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IP Leadership & External Engagement

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• Lead Strategic IP Development. Direct invention strategy and partner with IP engineering and patent counsel to build foundational patent portfolios supporting long-term licensing opportunities.
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• Develop Strategic Industry Partnerships. Build executive-level technical relationships with semiconductor companies, customers, foundries, EDA partners, universities, research organizations, and technical consultants to jointly explore emerging technologies, develop prototypes, and validate future architectures.
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• Represent Adeia Externally. Serve as Adeia’s technical authority in customer engagements, industry forums, technical collaborations, and strategic partnerships to strengthen the company’s leadership in emerging semiconductor technologies.
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Enterprise Technology Leadership

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• Drive Enterprise Technology Alignment. Align Discovery Engineering, R&D, IP Engineering, Product Engineering, and executive leadership around memory logic innovation priorities, ensuring coordinated execution of the technology roadmap.
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• Guide Technical Direction Across the Organization. Influence architectural decisions, technology standards, and innovation priorities across engineering organizations while mentoring senior technical contributors and fostering technical excellence without direct managerial responsibility.
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• Shape Future Innovation Programs. Identify emerging opportunities and develop proposals for new technology initiatives that strengthen Adeia’s long-term semiconductor strategy and competitive differentiation.
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Key Competencies

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• Demonstrates strategic thinking and long-term business perspective.
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• Builds credibility through deep technical expertise and sound judgment.
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• Influences and collaborates effectively across organizations without direct authority.
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• Drives innovation through curiosity, creativity, and continuous learning.
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• Builds trusted relationships internally and across the semiconductor ecosystem.
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Minimum Qualifications

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• Master’s or PhD in Electrical Engineering, Computer Engineering, Physics, or a related field.
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• 15+ years of experience in semiconductor architecture, memory systems, advanced logic design, or related technologies.
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• Deep expertise in memory logic integration, transistor technologies, and physical implementation.
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• Significant experience in standard cell design, circuit layout, and place and route.
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• Experience defining technology roadmaps and evaluating emerging semiconductor technologies.
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• Experience developing foundational inventions, patents, or advanced semiconductor technology concepts.
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• Experience leading cross-functional technical programs and influencing engineering strategy across multiple organizations.
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• Experience collaborating with semiconductor companies, customers, foundries, or ecosystem partners to develop and validate advanced technology concepts.
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Preferred Qualifications

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• Experience with heterogeneous integration, advanced packaging, or 3D integration.
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• Experience in compute-in-memory, memory-in-compute, or advanced memory architectures.
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• Experience working closely with IP engineering and patent development.
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Location: Remote US

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National Range: $195,000 - $245,000

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Bonus Target: 20% of annualized base pay

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Restricted Stock Units Target (as a % of annualized base pay): 75%

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The base compensation is based on the primary work location, as ranges are location-specific. Actual compensation will depend on factors such as skills, experience, and qualifications.

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Benefits include medical, dental, vision, 401(k), paid time off, and other company programs.

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Life @ Adeia:

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At Adeia, we are dedicated to creating a workplace where all employees have a voice and

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sense of belonging, feel safe and valued, and are acknowledged for how their unique

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differences contribute to organizational culture and business outcomes.

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Our employees and their families are important to us, and our comprehensive pay, stock,

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and benefits programs reflect that. Adeia supports personal well-being, builds financial

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security, and enables employees to share in our collective success.

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Rewards include:

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• Competitive compensation (salary, equity, and bonuses) and comprehensive benefits are designed to foster work-life balance, care for your health, protect your finances, and help you save and invest for the future.
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• Generous paid time away from work, including flexible time off, holidays and sick time, health and wellness initiatives, and a charitable match program to help you give back to your community.
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• Great benefits, which vary by location and can be site-specific: employee discounts, transportation reimbursements, and fitness facilities.
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• A flexible, hybrid work environment combining the best of in-office collaboration and community-building along with the benefits of working from home.
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