MAT Ramp: Digital Design Engineer - P3

Indotronix is seeking a Digital Design Engineer (P3) MAT Ramp for a job opportunity in Tucson, AZ.




Job Title: MAT Ramp: Digital Design Engineer - P3
Location: Tucson, AZ 85756
Duration: 12 Months Contract
Pay Rate: $100/hr on W2
1st shift: 9/80 schedule

Note: Need Active security clearance

Job Description
The Digital Design Engineer is responsible for the design, analysis, simulation, test, and integration of digital electronic modules and/or CCAs for Missile applications. The candidate should be experienced in all aspects of circuit card design including hardware designs with processors, FPGAs, memory, and industry interfaces, such as PCIe, Ethernet, I2C, SPI, and UART. The candidate will be working in a collaborative team environment.

Day to day Requirements:
Creation & Analysis
Parts Selection & trade studies
Architecture design block diagrams, etc.
Schematic Capture & Involvement with the Physical Layout process
Lab checkout & integration of HW utilizing test plan and lab equipment

Qualifications You Must Have:
Minimum 5 years of experience in the development and design of electronics circuit designs, multi-assembly system/unit design
Proficiency with electronic design and simulation tools across schematic creation, layout, and signal/power integrity analysis
Experience developing and supporting complex, multi layer circuit card assemblies