Senior ASIC Clocks IP Engineer - RTL to Silicon
NVIDIA Corporation
NVIDIA Corporation in Santa Clara, CA seeks a Senior ASIC Design Engineer for Clocks IP to architect clock domains for GPUs/CPUs, collaborating with front-end, floorplanning and back-end teams to meet timing, PPA and DFT requirements. Role involves implementing clocking topologies in RTL, evaluating trade-offs across DFx, physical implementation and power, and aiding silicon bring-up with verification teams. 3+ years in RTL design and strong Python scripting are required. #J-18808-Ljbffr NVIDIA Corporation
Vacancy posted 1 day ago
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