Verification Engineer Senior

Job Overview Intel is seeking a highly qualified candidate to join our ASIC design verification team in a dynamic and forward‑thinking organization focused on next‑generation semiconductor product development. Key Responsibilities Define Project Specific Verification Strategy: Define and implement scalable and reusable verification plans, test benches, and verification environments for blocks, subsystems, and SoCs, ensuring required coverage levels and compliance with microarchitecture specifications. Lead Verification Execution: Create detailed test plans, drive technical reviews with design and architecture teams, implement and run block/subsystem/cluster/SoC simulation models, analyze power and performance, and identify bugs. Investigate and Resolve Bugs: Replicate, root‑cause, and debug issues in the pre‑silicon environment, and implement corrective measures to resolve failing tests. Collaborate Across Teams: Work closely with SoC architects, micro‑architects, full‑chip architects, RTL developers, post‑silicon, and physical design teams to improve verification of complex architectural and microarchitectural features. Enhance Future Verification Methodologies: Continuously improve functional verification infrastructure and methodologies, incorporate post‑silicon learnings, update test plans for missing coverages, and proliferate improvements to future products. Lead and Mentor Others: Inspire and guide junior engineers, fostering their growth and development. Job Details Job Type: Experienced Hire Shift: Shift 1 (United States of America) Primary Location: US, Texas, Austin Qualifications Minimum Qualifications: Bachelor’s degree in Electrical Engineering, Computer Engineering, Computer Science, or a related STEM field with 6+ years of experience in ASIC/FPGA design verification, or Master’s degree with 4+ years of experience in ASIC/FPGA design verification. Object‑Oriented Programming (OOP) principles and their application in SystemVerilog UVM or other verification methodologies. Development of UVM and/or Formal‑based verification architectures and methodologies. Experience with industry‑standard protocols (AMBA AXI/AXI‑S/CHI and low‑speed communication protocols such as UART, SPI, I2C/I3C). Familiarity with coverage‑driven verification, constrained‑random testing, and strong debugging skills. Preferred Qualifications Graduate/post‑graduate degree in electrical engineering, computer engineering, computer science, or any STEM related degree with overall 6+ years of experience. Skill in various validation concepts and debug techniques relevant to the ASIC/FPGA domain. Hands‑on experience with simulators such as Synopsys VCS, Cadence Xcelium, or equivalent. Experience with scripting languages. EEO Statement All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance. Benefits We offer a total compensation package that includes competitive pay, stock bonuses, and benefit programs that include health, retirement, and vacation. #J-18808-Ljbffr Intel Corporation