Design Verification Engineer

Design Verification Engineer

Location: CA – Contract

Requirements:

• 6+ years of hands-on DV experience in object-oriented programming in SystemVerilog/UVM.
• Must be able to own and drive the verification of a block / subsystem or a SOC.
• Extensive experience in IP/sub-system and/or SoC level verification based on SV/UVM.
• Experience in Test plan and Testbench development,
• Execution of test plan using high quality constrained random UVM tests to hit coverage goals on time.
• Should be good with debugging and exposed to all aspects of verification flow including Gatesims