Principal Design Engineer

At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology.

Design Verification expert with good subsystem and SOC level verification . Must possess excellent debug skills. Expert in developing SV UVM based testbenches. Ability to coach and mentor less experience teammates. Should have worked on time-bounded projects leading to Si realization.

Independently handle verification of complex modules or own significant piece in subsystem / SOC based verification. Define methodology for subsystem/SOC verification. Mentor less experienced engineers to bring them up as independent verification engineer. Follow systematic approach of metric driven verification with meticulous attention to quality and completeness. Should be able work closely across teams to meet delivery timelines.

Required experience

• Worked on Subsystem / SOC level verification projects

• Experience in ARM based designs.

• In-depth knowledge SV-UVM

• Expertise in architecting, design and development of scalable verification environments from scratch. Define verification architecture and verification strategy

• Expertise in verification test plan development, test cases coding; Execute and debug test cases to achieve functional and code coverage goals

• Experience in C based testcase development

• Strong knowledge of AMBA protocols like AXI, ACE, APB, AHB.

• Good knowledge of at least one of the USB/PCIE/Ethernet/DDR/LPDDR or similar protocols

• Strong problem solving skills. Exhibit discipline, thoroughness and methodical approach in solving problems

• Ability to work with stakeholders across cross-functional teams - Architecture, Design, Internal and External Customers

• Experience in mentoring junior engineers

• Self-driven and committed individual who can work in a fast paced project environment

Desirable skills and experience

• Prior experience with Cadence tools and flows is highly desirable

• Familiarity with ARM/CPU architectures is a plus

• Experience in developing c-based test cases for SOC verification

• Experience with assembly language programming

• Good knowledge of some of the protocols like UART, I2C, SPI, JTAG

• Embedded C code development and debug

• Formal Verification experience

• Cadence verification tool experience

Strong vocabulary, communication, organizational, planning, and presentation skills are essential. Ability to work independently and productively with high quality output and results in a fast paced and dynamic environment. A strong positive attitude and ability to work in a team is a must. Self-motivated and willing take up additional responsibilities to contribute to team's success.

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Cadence plays a critical role in creating the technologies that modern life depends on. We are a global electronic design automation company, providing software, hardware, and intellectual property to design advanced semiconductor chips that enable our customers create revolutionary products and experiences.

Thanks to the outstanding caliber of the Cadence team and the empowering culture that we have cultivated for over 25 years, Cadence continues to be recognized by Fortune Magazine as one of the 100 Best Companies to Work For. ? Our shared passion for solving the world's toughest technical challenges, our dedication to pushing the limits of the industry, and our drive to do meaningful work differentiates the people of Cadence.

Cadence is proud to be an equal opportunity employer. All qualified applicants will receive consideration for employment without regard to race, color, sex, age, national origin, religion, sexual orientation, gender identity, status as a veteran, basis of disability, or any other protected class.

Cadence is committed to creating a diverse environment and is proud to be an equal opportunity employer. All qualified applicants will receive consideration for employment without regard to race, color, sex, age, national origin, religion, sexual orientation, gender identity, status as a veteran, basis of disability, or any other protected class.