Staff Engineer, Memory Systems Architecture

Staff Engineer, Memory Systems Architecture

San Jose, California, United States

Samsung Semiconductor is hiring now for a Staff Engineer, Memory Systems Architecture. The conventional DRAM failure analysis was physical electrical FA and physical FA. But, in the era of Data center, it is easier to track the field failure information. With this data set, Fault management team’s role is finding DRAM failure mode, abnormality and failure rate projection.

You will be part of an incubation team working on in-field telemetry intended to transform the Customer Quality Experience for Samsung memory products. Fault Management is the future of quality to minimize system downtime within AI/ML hardware deployments and workloads of the future. We analyze trends and patterns from enormous memory fleet telemetry to bucketize failures and perform virtual root-cause analysis. Telemetry analysis helps us design solutions to proactively avoid system downtime. We conduct research and develop both in-house and collaboratively in the industry with the opportunity to publish our findings through whitepapers and conferences. We are looking for innovative and passionate thinkers who can work in a start‑up environment and are excited to shape the future of data centers around the world. Join us in our mission!

What You'll Do

• Based on the knowledge of SOC controller and memory operation including RAS feature, find and recommend better solution to mitigate the field DRAM failure rate.
• Communicate better ECC scheme to customers based on Samsung DRAM failure mode (DQ and burst).
• Interface with customers to establish the value add of enabling in-field fault management architecture.
• Contribute to the standardization of DRAM/HBM failure logging in the OCP.
• Propose and develop platform RAS (Reliability Availability Serviceability) algorithms for memory fault management such as page offlining, hPPR and conduct POC with known failure DIMMs in the real server and application.

Location: Daily onsite presence at our San Jose headquarters in alignment with our Flexible Work Policy.

Job ID: 42886

What You Bring

• Bachelor’s degree with 10+ years of relevant industry experience, or Master’s with 8+ years or PhD with 5+ years hardware fault management, reliability, data center fleet management experience or related technical field preferred. (Must)
• Knowledge of platform memory subsystem, platform RAS (Reliability Availability Serviceability) such as ECC, page offlining, hPPR and hardware sparing.
• ECC design and verification and reverse engineering experience.
• Understanding of the address mapping between CPU and memory.
• Memory controller register modification.
• DRAM and HBM failure mode understanding.
• Inclusive mindset, adapting style to situations and diverse global norms.
• Avid learner, approaches challenges with curiosity and resilience, seeks data to help build understanding.
• Collaborative, builds relationships, offers support and welcomes approaches.
• Innovative and creative, proactively explores new ideas and adapts quickly to change.

Base Pay Range: $163,000 - $253,000 USD

Equal Opportunity Employment Policy

Samsung Semiconductor takes pride in being an equal opportunity workplace dedicated to fostering an environment where all individuals feel valued and empowered to excel, regardless of race, religion, color, age, disability, sex, gender identity, sexual orientation, ancestry, genetic information, marital status, national origin, political affiliation, or veteran status.

When selecting team members, we prioritize talent and qualities such as humility, kindness, and dedication. We extend comprehensive accommodations throughout our recruiting processes for candidates with disabilities, long-term conditions, neurodivergent individuals, or those requiring pregnancy‑related support. All candidates scheduled for an interview will receive guidance on requesting accommodations.