Sign up to access all features of our service.
  • Job search
  • Favorites
  • Create a CV
    New
  • Salaries
  • Subscriptions

Senior Staff Engineer, SoC Architecture - Memory Subsystem and Interconnect

$197.8k - $296.6k

Samsung Research America Cafe

Senior Staff Engineer, SoC Architecture – Memory Subsystem and Interconnect

The Samsung Research America SOC Architecture Lab provides innovative SoC architecture, bus / memory subsystem, multimedia subsystems and key IP blocks for future Samsung Galaxy products (Smartphones, tablets and future devices). We are defining the high-performance SoC architecture development for various Galaxy device lineups. This lab collaborates with Samsung’s strategic SoC partners, Samsung MX headquarter team, and key R&D teams around the globe to innovate and reinvent technology that will positively impact millions of people around the world via the Galaxy flagship products.

We are looking for a SOC Architect Fabric, System Cache and DRAM Controller to help architect next generation SOCs. This is a highly visible hands‑on role leading individual and team contributions to Fabric, System cache and DRAM controller sub‑system architecture, interface, performance and power tradeoffs.

Position Responsibilities

  • Guide on development of innovative Fabric, System cache and DRAM controller Architectural and microarchitectural features to boost power and performance on various targeted workloads in next generation SOCs
  • Identify and deliver Fabric, System cache and DRAM controller subsystem architecture proposals for products in new and existing markets
  • Evaluate architecture proposal benefits in collaboration with team of SoC Architects and communicate the results across related engineering audiences (SW, HW, Architecture, Leadership)
  • Perform high-level performance modeling/simulation and analysis of Fabric, System cache and DRAM controller features, applications, benchmarks, and complex uses cases
  • Direct and orchestrate performance modeling, and studies to support inclusion of these features in the next generation “Fabric, System cache and DRAM controller” microarchitecture based on performance, area or power improvement
  • Deliver architecture/microarchitecture proposals and specifications to the design team and articulate them effectively across audiences ranging from hardware & software engineers to architecture community peers, and to technology leadership
  • Collaborate with silicon bring‑up and product teams to verify and debug the proposal and its delivered performance
  • Collaborate across teams to bring microarchitectural proposals to fruition across the SOC, Driver, OS, System through detailed documentations

Required Skills

  • BSc, Masters, or PhD in Computer Science/Engineering, or equivalent combination of education, training, and experience
  • 12+ years of experience in SOC or ASIC design and architecture
  • Prior direct experience (> 9 years) in Fabric, System Cache, DRAM controller Architecture or microarchitecture is required
  • Understanding of memory controller architecture, memory scheduling, prioritization and QoS
  • Detailed knowledge of ARM bus infrastructure (ACE/AXI/AHB)
  • Fluid knowledge of one or more JEDEC standards such as LPDDR, DDR, or HBM, and the ability to analyze such standards and drive recommendations
  • Background in memory systems and computer architecture to understand the tradeoffs among memory bandwidth, latency, performance, power, SoC area

Special Attributes

  • Experience with BookSim Simulator
  • Experience with Platform Architect

Compensation

Hourly Pay Rate Range

$197,800 - $296,600 USD

Essential Job Functions

This position will be performed in an office setting. The position will require the incumbent to sit and stand at a desk, communicate in person and by telephone, and frequently operate standard office equipment, such as telephones and computers.

Equal Employment Opportunity

Samsung Research America is committed to employing a diverse workforce, and provide Equal Employment Opportunity for all individuals regardless of race, color, religion, gender, age, national origin, marital status, sexual orientation, gender identity, status as a protected veteran, genetic information, status as a qualified individual with a disability, or any other characteristic protected by law.

For more information regarding protection from discrimination under Federal law for applicants and employees, please refer to Pay Transparency.

#J-18808-Ljbffr

Vacancy posted 1 day ago
Similar jobs that could be interesting for youBased on the Senior Staff Engineer, SoC Architecture - Memory Subsystem and Interconnect in Mountain View, CA vacancy
  • Samsung Electronics GmbH is seeking a Staff Engineer for SoC Architecture specializing in Memory Subsystem and Interconnect in Mountain View, CA. This hands-on role involves leading contributions to the architecture of Fabric, System Cache, and DRAM Controller subsystems... 
    Suggested

    Samsung Electronics GmbH

    Mountain View, CA
    1 day ago
  • Samsung Research America in Mountain View is seeking a Staff Engineer, SoC Architecture with expertise in memory subsystem and interconnect. This role involves leading the architectural design of next-generation SOCs, focusing on Fabric, System Cache, and DRAM controllers... 
    Senior

    Samsung Research America

    Mountain View, CA
    1 day ago
  • $203.7k - $305.5k

     ...Lab Summary The Samsung SoC Architecture Lab explores innovative SoC architecture, key IP blocks (CPU, GPU, NPU), bus / memory subsystem and multimedia subsystems for future Samsung...  ...audiences ranging from hardware & software engineers to architecture community peers, and... 
    Senior
    Work at office
    Local area

    Samsung Research America (SRA)

    Mountain View, CA
    1 day ago
  • $180.2k - $297.2k

     ...and ResponsibilitiesAs a Senior Staff GPU Design Verification Engineer - Subsystems, you will help shape the...  ...performance integrity, and architectural intent. You bring strong...  ...Nice to have:Knowledge of memory subsystem or coherent interconnects is a plus. Experience... 
    Senior
    Hourly pay
    Full time
    Relocation

    Samsung Semiconductor

    San Jose, CA
    3 days ago
  •  ...Clara is seeking an experienced engineer to join our ASIC design team focused on memory subsystem architecture. You will drive RTL/micro-...  ..., including calibration and interconnect strategies. You will...  ...efficient memory hierarchies for SOCs. #J-18808-Ljbffr Apple Inc.
    Senior

    Apple Inc.

    Santa Clara, CA
    17 hours ago
  •  ...drive customer success on the memory subsystem across our silicon...  ...review next-generation memory architecture and design to catch defects...  ...experience collaborating with engineers located in different sites...  ...closure.Memory Subsystem and Interconnect Expertise: Be the authority... 
    Senior
    Night shift

    AMD

    San Jose, CA
    1 day ago
  • $200k - $300k

     ...Principal ASIC Architect - Memory Systems & AI...  ...equityRequirements: ASIC Architecture, Memory Subsystems, CXL / NVLink / PCIe...  ...-bandwidth optical interconnects for XPU memory...  ...AI accelerators and SoCs. The role combines deep...  ...other architects and engineers, setting best... 

    CyberCoders

    Santa Clara, CA
    4 days ago
  • $135.9k - $201.13k

     ..., and carrier architectures, our innovative...  ...ImpactAs a Senior Staff Digital ASIC Design Engineer at Marvell, you...  ...Ethernet and optical interconnects. You’ll work...  ...to define SoC‑level specifications...  ...for complex subsystems, high‑speed...  ...engines, memory subsystems, and... 
    Senior
    Permanent employment
    Full time
    Internship
    Work from home

    Marvell

    Santa Clara, CA
    5 days ago
  • $151k - $251.8k

    ## Staff Engineer, GPU Memory ArchitectApply: On-site: 9808 Scranton...  ...the definition, architecture, and...  ...generation GPU memory subsystems and on‐chip interconnects for Samsung’s Exynos...  ...chipset.In this mid-to-senior individual contributor...  ...system‐on‐chip (SoC).* Build and... 
    Hourly pay
    Full time
    Relocation

    Samsung Electronics Perú

    San Jose, CA
    1 day ago
  • Samsung Research America is seeking a Senior Staff Engineer to lead architecture of memory subsystem and interconnect in next-generation SoCs. The role combines fabric, system cache and DRAM controller design with performance and power tradeoffs across workloads. You will... 
    Senior

    Samsung Research America

    Mountain View, CA
    1 day ago
  • Architect, a frontier AI lab for chip design, seeks a Founding Member of the Technical Staff to own the AI-driven memory subsystem RTL design for production silicon. You will shape the microarchitecture, define DDR/HBM controller interfaces, and drive high-bandwidth, low... 
    Senior

    Kindredventures

    Palo Alto, CA
    1 day ago
  • $182k - $273k

     ...Role: As a Principal SoC IP & Interconnect Architect , you will...  ...expertise and architectural leadership to define...  .../O and interconnect subsystems, navigating complex...  ...with CPU and compute-engine teams, aligning with...  ...Knowledge of cache-coherent memory systems , DMA... 
    Local area

    Ampere Computing

    Santa Clara, CA
    2 days ago
  • $198.2k - $297.2k

     ...ResponsibilitiesAs a Senior Staff GPU Design Verification Engineer - Formal...  ...help shape block and subsystem level formal verification...  ...gating mechanisms, and architectural intent. You bring...  ...Have:Knowledge of memory subsystem or coherent interconnects is a plus.Proficiency... 
    Senior
    Hourly pay
    Full time
    Relocation

    Samsung Semiconductor

    San Jose, CA
    5 days ago
  • Google is seeking a Senior Staff CPU Cache Subsystem Design Engineer to lead front-end design teams, define microarchitecture, and deliver...  ...-generation CPU subsystems across target SOCs. You will collaborate with architecture, software, verification, power, DFT, and physical... 
    Senior

    Google LLC

    Mountain View, CA
    1 day ago
  • Ampere Computing is seeking a Principal SoC IP & Interconnect Architect in Santa Clara, CA to...  ...You will steer high-performance I/O architectures and collaborate across systems, design...  ...You will lead architecture definition, subsystem interfaces, and trade-off decisions,... 

    Ampere Computing

    Santa Clara, CA
    2 days ago
  •  ...NVIDIA is seeking a Senior SoC Product Architect, Memory Ecosystem, to drive external memory strategy across DRAM and non-volatile memories for data center, automotive, client, and edge platforms. You’ll partner with memory vendors to align roadmaps, influence designs... 
    Senior

    Jobleads-US

    Santa Clara, CA
    3 days ago
  • $136k - $218.5k

     ...world. NVIDIA is looking for an Senior ASIC Design Engineer to join our Memory Subsystem Team!Whatyou'llbedoing:As a...  ...world-class solution. NVIDIA SOC Interconnects, ordering controllers and memory...  ...be responsible for the micro-architecture and design including RTL design... 
    Senior
    Full time

    Nvidia

    Santa Clara, CA
    2 days ago
  • $163k - $253k

     ...Semiconductor is hiring now for a Staff Engineer, Memory Systems Architecture. The conventional DRAM failure analysis...  ...You'll DoBased on the knowledge of SOC controller and memory operation...  ...(Must)Knowledge of platform memory subsystem, platform RAS (Reliability Availability... 
    Flexible hours

    Samsung Semiconductor

    San Jose, CA
    2 days ago
  •  ...RTL design leader to drive complex ASIC digital subsystems from concept to silicon. You will define architecture, translate requirements into clear specifications...  ..., Ethernet, UALink, and AMBA. Mentoring junior engineers and leading design reviews are also key responsibilities... 
    Senior

    Synopsys, Inc.

    Sunnyvale, CA
    7 hours ago
  •  ...high-performance, energy efficient AI compute. As Principal SoC IP & Interconnect Architect, you will define and integrate advanced SoC and...  ...IP for next-generation Ampere products. You will drive architecture decisions with system architects, design, verification, and... 
    Senior
    Flexible hours

    Ampere

    Santa Clara, CA
    7 hours ago
  • NVIDIA is seeking a Senior ASIC Design Engineer to join our Memory Subsystem Team in Santa Clara. You will collaborate with architects, verification, formal...  ...class memory subsystem solution. You will own micro-architecture and design, including RTL, synthesis and timing... 
    Senior

    NVIDIA

    Santa Clara, CA
    2 days ago
  • $250k - $304k

     ...Position: Sr. Principal Engineer, SoC Architect...  ...# of Openings: 0 Senior Principal Engineer,...  ...generation AI scale-up architectures. Role Overview...  ...high-speed interfaces, subsystem architecture, interoperability...  ...across compute, memory, interconnect, security, and... 
    Senior

    Ayar Labs

    San Jose, CA
    1 day ago
  • $163k - $253k

     ...Staff Engineer, Memory Systems Architecture San Jose, California, United States Samsung Semiconductor is hiring...  ...ll Do Based on the knowledge of SOC controller and memory operation...  ...Must) Knowledge of platform memory subsystem, platform RAS (Reliability... 
    Flexible hours

    Conductor

    San Jose, CA
    1 day ago
  • $164k - $264.5k

     .... Job Area: Engineering Group, Engineering...  ...experienced PCIe Subsystem Architect to help...  ...high-performance I/O architectures for next-...  ...Universal Chiplet Interconnect Express (UCIe), Non-Volatile Memory Express (NVMe), Ethernet...  ...for server-class SoCs and accelerator subsystems... 
    Senior
    Work experience placement
    Work from home

    Qualcomm

    Santa Clara, CA
    2 days ago
  •  ...intellectually honest—where continuous learning is part of the job. We've built the industry's first highly programmable in-memory computing architecture, applicable from cloud to edge. In this role, you'll work on a groundbreaking architecture alongside a highly... 
    Senior

    Entrada Ventures

    Santa Clara, CA
    1 day ago
  • $180k - $223k

     ...next‑generation AI scale‑up architectures. The ASIC Sr. Staff Engineer is responsible for the...  ...debug of complex digital subsystems within an electro‑optical digital SoC. You will work in a dynamic...  ...Hands‑on work with high‑speed interconnects and optical systems... 
    Senior

    Alumni Ventures

    San Jose, CA
    1 day ago
  •  ...innovations in Flash and advanced memory technologies, our...  .... Description An AI Interconnect Architect defines and engineers high-speed networking and...  ...specify innovative scale-out architectures for optimizing power,...  ...Collaboration: Work with SoC, package design, and software... 
    Senior

    Sandisk

    Milpitas, CA
    2 days ago
  •  ...seeking a seasoned SoC Architect with...  ...in System Architecture. You have had significant...  ...cost. This senior role will stretch...  ...top-thinkers and engineers alike, ready to...  ...following: Processors, Memory sub-system, Interconnects, Coherency, Multimedia, I/O subsystems, Clocks, Resets,... 

    AMD

    San Jose, CA
    4 days ago
  •  ...Research America in Mountain View seeks a SOC Architect for Fabric, System Cache and...  ...System cache and DRAM controller sub‑system architecture, interface, performance and power...  ...ASIC design and architecture with strong memory systems expertise and ARM interface knowledge... 
    Senior

    Samsung Research America (SRA)

    Mountain View, CA
    1 day ago
  • Marvell is seeking a seasoned SoC design engineer to lead integration of internal and external IP blocks within the SOC team in Santa...  ...clock/reset, CDC, and timing constraints, and familiarity with ARM protocols and interconnect architectures. #J-18808-Ljbffr Anysilicon
    Senior

    Anysilicon

    Santa Clara, CA
    2 days ago

Do you want to receive more vacancies?

Subscribe and receive similar vacancies to Senior Staff Engineer, SoC Architecture - Memory Subsystem and Interconnect. Be the first to apply!