Senior RTL Architect for AI Accelerator (Equity Eligible)
DensityAI
DensityAI is seeking a seasoned RTL design engineer to own the design of digital blocks for our AI accelerator. You will oversee microarchitecture, SystemVerilog implementation, and integration, translating architectural specs into synthesizable RTL that meets PPA targets. You will collaborate with DV, PD, and DFT teams across the RTL2GDS flow to tape out silicon, while leveraging Python/Tcl for automation and tackling advanced interconnects and memory subsystems. #J-18808-Ljbffr DensityAI
Vacancy posted 4 days ago
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