Senior Memory Subsystem RTL Architect for AI Chips
Architect Labs
Architect Labs seeks a founding member for RTL design of the memory subsystem powering AI workloads. You will own memory controllers, hierarchy, and near-memory accelerators, collaborating with DV, SW, and ML teams to hit bandwidth, latency, and power goals. Strong SystemVerilog, DDR/HBM knowledge, and Python tooling are essential, with experience in high-frequency controller logic and tapeouts. #J-18808-Ljbffr Architect Labs
Vacancy posted 3 days ago
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