SoC Physical Design Engineer, Senior Member of Technical Staff (SMTS)

SoC Physical Design Engineer In the Heterogeneous Integration Group (HIG), the engineer drives advanced HBM SoC logic/base die implementations from netlist to GDSII, collaborating closely with RTL design, verification, DFT, IP providers, packaging/assembly, and manufacturing teams to deliver best‑in‑class PPA and robust signoff collateral for tapeout. This is a hands‑on role with opportunities to own blocks or top‑level integration across multiple product generations. Key Responsibilities Own physical implementation for SoC blocks and/or top‑level, including floor planning, placement, CTS, routing, and physical optimization to meet PPA targets. Drive timing closure (setup/hold) across multi‑mode/multi‑corner scenarios; partner with RTL, architecture, and STA/signoff to converge designs. Collaborate with design and integration teams to ensure clean implementation of clocking/reset strategy, power architecture, and SoC integration requirements. Integrate and implement complex IP (e.g., controllers, microcontrollers, NOC, interfaces, MBIST/DFT logic, buffers, PHY‑adjacent logic) with focus on robust physical integration and timing/power integrity. Perform and/or coordinate physical signoff, including DRC/LVS, IR drop/EM, and timing signoff, addressing violations efficiently. Work with packaging, assembly, test, probe, and manufacturing stakeholders to ensure design meets manufacturability and quality requirements. Support tapeout execution (checklists, ECO flows, signoff reviews) and contribute to post‑silicon debug by correlating silicon behavior with PD/STA/power analysis. Identify flow gaps and improve productivity through scripting/automation and best‑practice methodology development. Required Qualifications Strong experience in SoC physical design implementation from netlist to GDSII on advanced nodes and complex designs. Proficiency with industry EDA tools (e.g., Cadence Innovus/Tempus, Synopsys ICC2/PrimeTime, Siemens Calibre or equivalent). Experience with power intent and power delivery considerations (e.g., UPF/CPF concepts, power grid planning, power gating implications). Exposure to hierarchical physical design, top‑level assembly, partitioning guidelines, and large‑scale integration methodology. Knowledge of IR/EM analysis, noise, coupling/crosstalk considerations, and mitigation strategies. Proven tapeout history on advanced foundries (e.g., TSMC) and understanding of full‑cycle SoC development flows. Strong scripting/automation skills using Python, TCL, Perl, and/or shell. Preferred Qualifications Experience with HBM/DRAM adjacent SoC designs, or memory‑subsystem‑heavy SoCs. Bachelor’s or Master’s degree in Electrical Engineering, Computer Engineering, or a related field. Minimum 15 years of experience in a related field. Compensation U.S. base salary range: $177,000.00 – $334,000.00 per year. Benefits Micron offers medical, dental, vision, income protection, paid family leave, paid time‑off, and paid holidays. EEO Statement Micron is proud to be an equal‑opportunity workplace and is an affirmative action employer. All qualified applicants will receive consideration for employment without regard to race, color, religion, sex, sexual orientation, age, national origin, citizenship status, disability, protected veteran status, gender identity or any other factor protected by applicable federal, state, or local laws. #J-18808-Ljbffr Micron Technology