Senior Director, SerDes Digital Design

Job Description

Job Description

Why join Upscale, Inc. 

Upscale, Inc., is building the high-performance infrastructure powering the next generation of artificial intelligence. Backed by over $500M in funding and rapid global adoption, we are scaling systems designed for the world’s most demanding AI workloads.

We focus on first-principles engineering across silicon, systems, and networking—where performance, scale, and execution are critical. Our team is talent-dense and high-performing. We value ownership, technical rigor, and speed, and we offer the opportunity to work on foundational problems with immediate, real-world impact.

If you’re looking to do high-impact work, move fast, and help define the infrastructure behind the future of AI—Upscale is where you can produce meaningful work at the frontier—and operate at a high standard. 

About the Role

We are building a world-class SerDes engineering organization to enable next-generation, ultra-high-speed connectivity for AI data centers and high-performance computing. We are seeking an experienced Senior Director of SerDes Digital Design to lead the architecture, development, and implementation of the digital subsystem for next-generation SerDes technologies.

The SerDes digital subsystem plays a critical role in overall PHY performance, supporting digital signal processing (DSP) and equalization, performance calibration, PHY initialization and adaptation, and control and monitoring functions. The successful candidate will bring proven experience delivering digital functionality for 100G+ per-lane SerDes, combined with the technical depth and leadership skills needed to drive complex, power-efficient, and high-performance silicon.

In this role, you will work closely with DSP, analog, system architecture, verification, and silicon validation teams to define digital architecture and deliver robust, production-quality SerDes solutions. You will also build and develop a strong engineering organization capable of delivering the digital technologies required for future generations of high-speed connectivity.

Responsibilities:

• SerDes Digital Architecture: Define and drive the digital architecture for next-generation SerDes PHYs, aligning DSP, calibration, initialization, adaptation, and control functions with overall system performance requirements.
• DSP and Signal Equalization: Lead the development and integration of digital signal processing functions supporting high-speed link performance, including transmit and receive equalization, adaptation algorithms, and related datapath processing.
• Analog and Mixed-Signal Calibration: Drive digital architecture and implementation for analog calibration and compensation, including calibration sequencing, control algorithms, coefficient management, and background or foreground calibration mechanisms.
• PHY Initialization and Adaptation: Own digital initialization, configuration, training, adaptation, and control sequences required to bring up and maintain robust high-speed links across process, voltage, temperature, and channel variations.
• Digital Verification and Quality: Establish rigorous design and verification practices to ensure functional correctness, robust corner-case handling, and predictable integration and silicon bring-up.
• Cross-Functional Integration: Partner closely with analog, receiver, transmitter, clocking, system architecture, firmware, and silicon validation teams to deliver a cohesive end-to-end SerDes solution.
• Silicon Bring-Up and Debug: Lead digital support for silicon bring-up, characterization, calibration, and production readiness, driving root-cause analysis of system-level issues across digital and analog boundaries.
• Team Building and Technical Leadership: Build, recruit, mentor, and lead a high-performing SerDes digital engineering team, developing technical leaders and establishing a culture of ownership, technical excellence, and execution.
• Technology Roadmap: Establish the digital technology roadmap for future SerDes generations, identifying architectural improvements in DSP, calibration, control, power efficiency, and implementation scalability.

Qualifications:

• BS, MS, or PhD in Electrical Engineering, Computer Engineering, or a related field.
• Extensive experience in digital IC design, with significant technical and organizational leadership responsibilities.
• Proven experience designing and delivering digital functionality for 100G+ per-lane SerDes PHYs.
• Strong understanding of high-speed SerDes architecture and the interaction among digital signal processing, analog front-end circuits, clocking, calibration, and link adaptation.
• Demonstrated experience leading complex RTL development, digital implementation, integration, and silicon delivery.
• Strong knowledge of digital design methodologies, including microarchitecture, synthesis, timing closure, clock-domain crossing, low-power design, and design-for-test considerations.
• Experience driving digital verification and system integration for complex mixed-signal products.
• Proven ability to lead multidisciplinary engineering efforts, resolve challenging technical issues, and deliver production-quality silicon.
• Demonstrated ability to recruit, develop, and retain strong engineering talent while building a collaborative, high-performing organization.

• Experience delivering SerDes digital subsystems across multiple product generations or into production volume.
• Experience with high-performance SerDes DSP architectures, including equalization, digital filtering, adaptation, and coefficient-update mechanisms.
• Experience implementing digital calibration and control for high-speed analog and mixed-signal circuits, including ADCs, DACs, PLLs, clocking circuits, and transmitter or receiver front ends.
• Understanding of high-speed link training, initialization, adaptation, diagnostics, and link-management requirements.
• Experience optimizing digital architectures for demanding power, performance, and area targets in advanced process technologies.
• Experience with advanced-node semiconductor development, complex PHY integration, silicon characterization, and production ramp.
• A strong track record of building engineering teams and delivering competitive high-speed connectivity products.

Where you fall within that range depends on your experience, skills, and impact—we benchmark against internal levels to keep things fair and consistent.

Equal Opportunity

Upscale, Inc., is building a team that reflects a wide range of perspectives, backgrounds, and experiences. We’re proud to be an Equal Opportunity Employer and consider all qualified applicants regardless of race, color, religion, national origin, sex, sexual orientation, gender identity, disability, or veteran status.

Accessibility & Accommodations

We’re committed to making our hiring process accessible to everyone. If you need accommodations at any stage, just reach out to us at  View email address on ziprecruiter.com —we’re happy to help. Note: This inbox is only for accommodation requests.

We may use artificial intelligence (AI) tools to support parts of the hiring process, such as reviewing applications, analyzing resumes, or assessing responses and identifying potential inconsistencies or verification signals in application materials based on available information. These tools assist our recruitment team but do not replace human judgment. Final hiring decisions are ultimately made by humans. If you would like more information about how your data is processed, please contact us.