Senior PLL & Analog Designer (RF/Serdes)
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Samsung Semiconductor Inc. in San Jose, CA, is seeking a Senior/Staff PLL Designer to develop high-performance PLLs and clocking subsystems for RF transceivers and high-speed I/O in deep-submicron CMOS.
You will collaborate with digital and software teams, perform system modeling, verification, and production support, and contribute to layout and lab testing to meet stringent requirements.
#J-18808-Ljbffr Jobleads-USVacancy posted 1 day ago
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