Lead SoC Design Engineer - Edge AI, High-Performance ASIC

Job Title: Lead SoC Design Engineer - Edge AI, High-Performance ASICJob Location: San Francisco, CA or Los Altos, CA - hybridCompensation: $300K - $425K base DOE plus equityRequirements: SoC Microarchitecture, RTL Design, IP Integration (UCIe, DDR, CPU/GPU/NPU), ARM Cores, Memory Subsystems, AMBA Protocols (CHI, AXI, ACE, APB), HPC / Edge AI SoCPosition OverviewWe're a well-funded, stealth startup building a next-generation, end-to-end computing platform powered by a custom, high-performance edge SoC on an advanced process node. By integrating flagship compute IP into an industry-leading design, we are building the optimized silicon foundation for our software platform from the ground up.We're building a tight-knit, experienced in-house team to drive engineering outcomes and partner with a Tier-1 ASIC design house through the process. As our Lead SoC Design Engineer, you will develop the microarchitecture, own the critical tradeoffs required to hit aggressive PPA targets, and spearhead the implementation of key subsystems.Key ResponsibilitiesMicroarchitecture: Author detailed microarchitecture documents and drive reviews with software, architecture, and verification teams.Drive PPA targets: Since we are developing a power-sensitive client product, you will drive performance/power tradeoffs using a data-driven approach to hit aggressive targets.Partner with the verification team: Participate in reviews of verification and emulation test plans to ensure successful first-pass silicon.RTL design: Own RTL coding, Lint/CDC/RDC checks, SDC and VCLP checks, and ensure that the design can be taken through physical design to meet frequency and power requirements.QualificationsBachelor's or Master's degree in Electrical Engineering, Computer Engineering, Computer Science, or related field; advanced degree preferred.10+ years of experience in developing complex ASICs in advanced nodes.Deep knowledge of industry-standard on-chip interconnect protocols (AMBA AXI/AXI-S/APB)Experienced with Verilog, SystemVerilog, SystemVerilog Assertions (SVA).Proficiency in writing and debugging SDC timing constraints, including multi-cycle paths, false paths, and clock domain crossing constraints.Experience with industry-standard ASIC CAD tools for simulation, synthesis, STA, Lint, LEC, CDC, RDC, and power estimation.Experience designing with multiple power domains and UPF.Preferred QualificationsExperience with commercial IP integration, ranging from high-speed interfaces (UCIe, DDR) to processing subsystems (CPU, GPU).Experience working directly with ARM cores and subsystems.#EnghpBenefitsMedical/Dental/Vision benefitsVacation/PTO401KEquityFlexible Work Arrangements