Senior Director, CAD & Design Methodology

Build the Engineering System Behind the Next Generation of Physical AI About Velaura At Velaura, we’re building custom silicon for Physical and Embodied AI—robots, drones, autonomous systems, and intelligent machines that must perceive, reason, and act in the real world. Over the years, we have come to recognize that engineering productivity is a competitive advantage. The methodologies, infrastructure, automation, and design flows behind the scenes determine how quickly ideas become silicon. This role is an opportunity to build that engineering system from the ground up. You won’t inherit decades of legacy infrastructure—you’ll define how Velaura designs every chip for years to come. What You’ll Own Architect and own Velaura’s end-to-end ASIC development methodology—from the first line of RTL through physical implementation, signoff, packaging integration, and tapeout. Establish scalable, reproducible design flows across RTL, verification, synthesis, DFT, physical design, STA, physical verification, release management, and silicon bring-up support. Lead the evaluation, selection, deployment, and integration of best-in-class EDA tools across multiple vendors, balancing productivity, quality, flexibility, and cost. Define the company’s engineering infrastructure strategy, including compute, storage, networking, cloud resources, job scheduling, security, backup, and disaster recovery. Build automation frameworks, CI/CD pipelines, regression systems, dashboards, and engineering workflows that continually improve productivity and design quality. Own EDA licensing strategy, vendor relationships, procurement, budgets, IP administration, and license compliance. Partner with architecture, RTL, verification, physical design, packaging, software, and IT teams to remove friction and accelerate execution. Build, mentor, and scale a world-class CAD and methodology organization. What We’re Looking For Deep understanding of the complete ASIC development lifecycle, from architecture and RTL through tapeout. Experience developing and owning design methodologies across multiple successful SoC programs. Hands‑on experience with EDA ecosystems from multiple vendors such as Synopsys, Cadence, Siemens EDA, Ansys, and related tools. Strong understanding of engineering compute infrastructure, distributed scheduling, storage systems, cloud environments, and license management. Excellent scripting and automation skills using Python, Tcl, Bash, or similar. Strong knowledge of version control, continuous integration, regression management, and reproducible engineering practices. Ability to make sound technical and business decisions involving tools, infrastructure, budgets, licensing, and engineering investment. Exceptional organizational and leadership skills, with a passion for enabling other engineers to do their best work. Excellent communication skills and the ability to influence senior technical leaders across disciplines. Nice to Have Experience with advanced technology nodes (N3, N2, or beyond). Experience building CAD organizations in an early‑stage semiconductor company. Familiarity with AI‑assisted engineering workflows and next‑generation design automation. Experience supporting chiplet‑based designs or advanced packaging. Compensation & Benefits At Velaura, we believe exceptional talent deserves exceptional rewards. Compensation for this role includes a competitive base salary, performance‑based incentives, and equity participation, allowing team members to share in the company’s long‑term success. The base pay range for this role is between $200k and $500k, and your base pay will depend on your skills, qualifications, experience, and location. In addition to compensation, Velaura offers a comprehensive benefits package that may include medical, dental, and vision coverage, paid time off, flexible work arrangements, professional development opportunities, and other benefits designed to support the well‑being and growth of our team. Velaura is committed to pay equity and transparency, and we regularly benchmark compensation to ensure we remain competitive in the market. Why Join Velaura? This is not a traditional CAD position. It is a company‑building role. You will influence every engineering team, every tapeout, every methodology decision, and every future chip we build. If you enjoy creating systems that allow exceptional engineers to move faster, collaborate better, and deliver world‑class silicon, we’d love to meet you. #J-18808-Ljbffr Velaura AI