Sign up to access all features of our service.
  • Job search
  • Favorites
  • Create a CV
    New
  • Salaries
  • Subscriptions

Senior STA Methodology Engineer — RTL-to-GDS Timing Leader

$120k - $220k

E-Space

E-Space, located in Saratoga, California, is seeking a Senior STA Engineer to lead efforts in solving complex timing challenges in their low Earth orbit satellite systems. The role requires over 8 years of industry experience, expertise in STA methodologies, and proficiency in scripting for CAD utilities. This full-time position offers a competitive salary range of $120,000 to $220,000, plus a comprehensive compensation package, including health and wellness options, continuous learning opportunities, and a commitment to sustainability. #J-18808-Ljbffr E-Space

Vacancy posted 2 days ago
Similar jobs that could be interesting for youBased on the Senior STA Methodology Engineer — RTL-to-GDS Timing Leader in Saratoga, CA vacancy
  • $120k - $220k

     ...quality of life. We are seeking a Senior STA Methodology Engineer to join our ASIC design team. In...  ...role, you will own cross-functional timing methodology efforts across multiple...  ...enhance STA methodologies across the full RTL-to-GDS flow, including early timing... 
    Senior
    Full time
    Work at office
    Immediate start
    Visa sponsorship
    Night shift

    E-Space

    Saratoga, CA
    12 days ago
  • Insilico is seeking an experienced STA Engineer to join their team in Sunnyvale, CA. The ideal...  ...have over 10 years of experience in Static Timing Analysis and demonstrate proficiency with...  ..., and handling analysis related to RTL designs. Insilico values confidentiality... 
    Senior

    Insilico

    Sunnyvale, CA
    5 days ago
  • $100k

     ...looking for contributors of all seniorities. Tenstorrent is looking for a STA methodology engineer who owns timing across advanced‑node, high‑...  ...across the full RTL‑to‑GDS flow, including: Early timing...  ...and execution. A technical leader to architect, optimize, and... 
    Suggested
    Permanent employment

    Tenstorrent

    Santa Clara, CA
    2 days ago
  • E‑Space is seeking a Senior STA Methodology Engineer to own cross‑functional timing methodology across multiple IPs and nodes for SoC designs targeting 5G, IoT,...  ...Responsibilities include leading timing challenges, optimizing RTL‑to‑GDS flows, scripting production CAD utilities, and... 
    Senior

    Espace

    Saratoga, CA
    2 days ago
  • Qualcomm Atheros, Inc. is seeking a senior role focused on static timing analysis, synthesis, and low‑power implementation for complex WiFi SoCs. The position...  ...and multi‑corner/multi‑mode timing closure, working with RTL, synthesis, and physical design teams in a dynamic... 
    Senior

    Qualcomm

    Santa Clara, CA
    4 days ago
  • Tenstorrent Inc. is seeking a Static Timing Analysis (STA) Methodology Engineer in Santa Clara, CA. This hybrid role involves leading the development of STA methodologies across advanced-node designs, utilizing deep knowledge of timing tools and scripting skills. The ideal... 

    Tenstorrent Inc.

    Santa Clara, CA
    2 days ago
  • $100k

    A leading AI technology company is seeking a Static Timing Analysis (STA) Methodology Engineer to lead the development of advanced STA methodologies across various projects. This hybrid role requires extensive experience with STA tools like PrimeTime and strong scripting... 

    Tenstorrent Inc.

    Santa Clara, CA
    2 days ago
  • $100k

    A tech company is seeking a STA methodology engineer skilled in timing across advanced-node designs. This hybrid position requires a proven background in Static Timing Analysis and expertise with tools like PrimeTime. Candidates should be proficient in scripting with Tcl... 

    Tenstorrent

    Santa Clara, CA
    2 days ago
  • $120k - $220k

     ...Senior Design‑for‑Test Engineer Responsible for defining and implementing...  ...ordering, routing, and test timing Define and implement...  ...DFT specifications, methodology guidelines, and test...  ...physical design and STA teams for scan chain...  ...fundamentals and RTL design practices Passion... 
    Senior
    Full time
    Work at office
    Visa sponsorship

    eSpace

    Saratoga, CA
    1 day ago
  • $136k - $218.5k

    Responsibilities Drive timing analysis and closure for DFT logic...  ...experience) in Electrical or Computer Engineering with 5+ years’ experience or...  ...in Static Timing Analysis (STA) and driving timing...  ...IO, SMVA, etc. Experience in methodology and/or workflow development.... 
    Senior

    NVIDIA

    Santa Clara, CA
    2 days ago
  • $168k - $264.5k

     ...accelerated computing. We are seeking a Senior Timing Closure Engineer on our Circuit Solutions Group to...  ...timing convergence flows working with methodology teams. Develop timing models and methodology...  ...industry standard transistor level STA tools such as NanoTime and timing... 
    Senior

    NVIDIA AI

    Santa Clara, CA
    2 days ago
  • $168k - $264.5k

     ...We are now looking for a motivated Senior Timing Closure Engineer to join our dynamic and growing Circuit...  ...timing convergence flows working with methodology teams. Develop timing models and...  ...of industry standard transistor level STA tools such as NanoTime and timing convergence... 
    Senior

    NVIDIA

    Santa Clara, CA
    2 days ago
  • $229.6k - $237k

    Platforms and Devices Senior Silicon Engineer - SoC Front-End / RTL Design (multiple openings) Be part of a team that...  ...base salary range for this full-time position is $229,600 to $237,000...  ...Estimation). Contribute to development of methodology and tools, to improve the... 
    Senior
    Full time
    Work at office
    Worldwide

    Google

    Mountain View, CA
    2 days ago
  • $168k - $310.5k

    NVIDIA Gruppe is seeking a Senior P&R Methodology Architect to define the next generation RTL2GDS flow for cutting-edge designs. This role involves collaboration with core developers and requires deep expertise in physical design processes. Candidates should have experience... 
    Senior

    NVIDIA Gruppe

    Santa Clara, CA
    2 days ago
  • $136k - $218.5k

     ...Requisition ID: JR2000499 Job Category: Engineering Time Type: Full time NVIDIA has...  ...you will help develop and deploy DFT methodologies for our next generation products. You...  ...to cross‑functional areas including RTL & clocks design, STA, place‑n‑route and power, to ensure... 
    Senior
    Full time

    NVIDIA AI

    Santa Clara, CA
    21 hours ago
  •  ...is seeking an experienced ASIC Digital Signoff Engineer in sunny California. As part of the IP Digital Design Methodology team, you will define ASIC design standards and...  ...of hands-on experience, particularly in Static Timing Analysis and EM/IR flows, showcasing strong problem... 
    Senior

    Synopsys Inc

    Sunnyvale, CA
    2 days ago
  • $220k - $350k

    DensityAI in Mountain View, California is looking for a skilled professional to own full chip and block timing methodologies for their AI accelerator silicon. The role requires extensive experience in high performance designs and the ability to work closely with chip-design... 
    Senior
    Full time

    DensityAI

    Mountain View, CA
    2 days ago
  • Apple is seeking a Senior Simulation Animation Engineer to be part of an innovative team developing advanced simulation projects. You will work on impactful...  ...departments. Responsibilities include designing real-time animation systems and optimizing features for multiple... 
    Senior

    Apple

    Cupertino, CA
    2 days ago
  • Netflix is seeking motivated engineers for its Ads Platform Engineering team to develop and operate systems handling ads-related events....  ...paced environment. Ideal candidates possess strong skills in real-time systems, ad technologies, and APIs. Netflix offers a... 
    Senior

    Netflix

    Los Gatos, CA
    2 days ago
  • $100k

     ...for contributors of all seniorities. We are looking for a talented engineer to join our CPU design team...  ...with DV, PD, RTL and performance teams to deliver a functional, timing, and power‑converged design...  ...flows and physical design methodology. Background in CPU micro... 
    Senior
    Permanent employment

    Tenstorrent Inc.

    Santa Clara, CA
    5 days ago
  • $136k - $218.5k

     ...tools to benefit circuit design quality and reduce design‑cycle times. Take ownership of new EDA tool workflows: architecting,...  ...primarily Python and Perl). 5+ years of experience in circuit design methodology using Cadence/Synopsys systems (Virtuoso/Custom Compiler).... 
    Senior

    NVIDIA

    Santa Clara, CA
    2 days ago
  •  ...experienced professional in Sunnyvale, California, to lead static timing analysis for innovative TPU technology. The role involves...  ...teams. Candidates should have a Bachelor's degree in Electrical Engineering or a related field, along with extensive experience in static... 
    Senior

    Google

    Sunnyvale, CA
    4 days ago
  •  ...cutting-edge technology company is seeking a Sr. Staff HW Engineer for ASIC Implementation to lead RTL integration across DSP ASIC programs. The role...  ...flows, coordinating backend partnerships, and supporting timing closure. Strong experience in digital implementation,... 
    Senior

    Arycs Technologies, Inc.

    Los Gatos, CA
    2 days ago
  •  ...collaborate with Architects, ASIC Design Engineers, Low Power Engineers, Performance...  ...Responsibilities Define and implement tools and methodologies for efficient data generation from post...  ...of chip design process from RTL design to tape-out. Background in machine... 
    Senior

    NVIDIA

    Santa Clara, CA
    2 days ago
  •  ...seeking an experienced FPGA Verification Engineer based in Sunnyvale, California. The role...  ...FPGA's on daVinci systems focusing on RTL functional correctness and working closely...  ...will have advanced knowledge of UVM methodology and expertise in SystemVerilog. This position... 
    Senior

    Intuitive Surgical, Inc.

    Sunnyvale, CA
    2 days ago
  • $198.7k - $298.1k

     ...Qualcomm Technologies, Inc. Job Area: Engineering Group, Engineering Group CPU...  ...engineer who thrives at the intersection of RTL design and CAD automation. This role is...  ...Responsibilities Define and develop methodologies to build scalable, efficient CPU designs... 
    Work experience placement
    Work from home

    Qualcomm

    Santa Clara, CA
    2 days ago
  • $198.7k - $298.1k

     ...Qualcomm Technologies, Inc. Job Area: Engineering Group, Engineering Group CPU...  ...hiring talented engineers for RISCV CPU RTL development targeting high-performance, low...  ...understanding of logic design principles, including timing and power implications Preferred... 
    Senior
    Work experience placement
    Work from home

    Qualcomm

    Santa Clara, CA
    8 hours ago
  • Applications Engineering, Sr Staff Engineer- RTL-to-GDS/Fusion Compiler Join to...  ...synthesis, place & route, timing closure, and power...  ...verification methodologies. Contributing to...  ...and thought leader in physical design...  ...hiring process. Seniority level Mid‑Senior level... 
    Senior
    Full time

    Synopsys Inc

    Sunnyvale, CA
    2 days ago
  •  ...plus Collaborate with architects, hardware engineers, and firmware engineers to understand...  ...verified Understanding of Design for Test methodologies and DFT verification experience is a plus Proficient in debugging firmware and RTL code using simulation tools KEY... 
    Senior

    Infobahn Softworld Inc

    Santa Clara, CA
    5 days ago
  • $120k - $220k

    Espace is seeking an experienced EM/IR Analysis Engineer for a full-time position based in Saratoga, California. The role involves leading critical EM/IR drop analysis for complex SoC designs and collaborating with cross-functional teams to optimize power integrity strategies... 
    Senior
    Full time

    Espace

    Saratoga, CA
    2 days ago

Do you want to receive more vacancies?

Subscribe and receive similar vacancies to Senior STA Methodology Engineer — RTL-to-GDS Timing Leader. Be the first to apply!