Senior FPGA Verification Engineer - RTL, UVM & Coverage
Intuitive Surgical, Inc.
Intuitive Surgical, Inc. is seeking an experienced FPGA Verification Engineer based in Sunnyvale, California. The role involves verifying FPGA's on daVinci systems focusing on RTL functional correctness and working closely with the design team to develop test plans. The successful candidate will have advanced knowledge of UVM methodology and expertise in SystemVerilog. This position is fully onsite and offers competitive compensation based on qualifications and experience. #J-18808-Ljbffr Intuitive Surgical, Inc.
- ...worldwide. We’re a team of engineers, clinicians, and... ...Roles & Responsibilities Verification of FPGA’s on daVinci systems for RTL functional correctness Starting... ...closing verification using coverage metrics Hands‑on testbench development UVM Work closely with the design...SeniorLocal areaWorldwide
- Roles & Responsibilities Verification of FPGA's on daVinci systems for RTL functional correctness Starting from test-planning to closing verification using coverage metrics Hands‑on testbench development UVM Work closely with the design team to review specifications...SeniorLocal areaFlexible hoursShift work
- iFlow Inc. is seeking a Design Verification Engineer based in Santa Clara, CA, for a long... ...proficiency in SystemVerilog and UVM, alongside debugging skills. Key... ...environments for testing, performing coverage analysis, and collaborating with RTL designers to debug simulation...Senior
- ...System Verilog, and modern verification libraries like UVM 10+ years of ASIC design... ...with architects, hardware engineers, and firmware engineers to... ...in debugging firmware and RTL code using simulation tools... ...Work on functional and code coverage verification Provide...Senior
- STI is seeking a highly motivated FPGA Verification Engineer in Santa Clara, CA. In this role, you will develop verification plans for complex FPGA designs, ensuring functionality and reliability. You will collaborate closely with design engineers, execute verification...Senior
- ..., CA. The position requires extensive experience in FPGA design and verification, particularly with System Verilog and UVM methodologies. Candidates must have a Bachelor's or Master's degree in Electrical Engineering and over 10 years of relevant experience. This contract...SeniorContract work
$237k - $356k
...we’d love to have you apply! About The Role As a Senior Principal Emulation & FPGA Prototyping Verification Engineer, you will apply extensive, specialized expertise... .... Expert‑level proficiency in debugging complex RTL issues. Highly skilled in developing comprehensive...SeniorLocal area$119.8k - $258k
...technology company located in Mountain View, CA is seeking a Design Verification Engineer to support SoC-level verification of advanced high-speed and... ...experience and strong skills in SystemVerilog and UVM. This position offers a full-time employment opportunity with...SeniorFull time$150k - $165k
Encore Semi, Inc. in Sunnyvale, CA is seeking a Sr Design Verification Engineer to verify complex digital systems, including ARM-based CPUs and... ...the full verification lifecycle, utilizing SystemVerilog and UVM to ensure design quality and integrity. The anticipated annual...Senior- ...provider of SoC ASIC/FPGA and Embedded... ...Prodapt ASIC BU: SoC/ASIC RTL Design, UVM based verification, Emulation, FPGA based... ...are looking for a Senior Design Verification... ...random, directed, and coverage-driven test scenarios... ...with design engineers to resolve issues. Drive...Senior
- ...your career. The Role As a Senior CPU Design Verification Engineer, you will join a CPU... ...using C++, SystemVerilog, and UVM Collaborate with design, verification... ...quality metrics and coverage closure Support... ...and UVM Familiarity with RTL design (Verilog or equivalent...Senior
$136k - $218.5k
...seeking best-in-class ASIC Verification Engineers to verify the world’s leading... ...testbench Partner closely with RTL and architecture teams to... ..., test planning, coverage closure, and test bench design... ...Unified Verification Methodology (UVM), SystemVerilog checkers and...SeniorShift work- ScOp Venture Capital is looking for a Senior Design and Verification Engineer to work on cutting-edge AI systems for EDA. You will collaborate closely with... .... The ideal candidate has a strong background in RTL design, functional verification, and experience with simulation...Senior
$128k - $258.75k
...hardworking and creative Senior Memory Controller Verification Engineer for our Tegra SoCs!... ...regressions, close coverage and sign off design... ...coverage of all the RTL which you will... ...Work with and enable FPGA and software teams to... ...System Verilog and UVM based methodology for...Senior- ...self-motivative Design Verification Engineer to join our growing... ...and help our experts in RTL, FW, circuit, and architecture... ...on functional & code coverage verification. Provide... ...libraries like UVM 10+years of ASIC design... ...Electrical Engineering Seniority level Mid-Senior level...Contract workWork at office2 days per week3 days per week
- Job Openings (Mid/Sr/Princ) Verification Design Engineer (UVM) About the job (Mid/Sr/Princ) Verification Design Engineer (UVM) In this role, you will... ...testbenches, tests, regressions, and functional coverage to achieve zero bug escapes. The UVM environment will co...Senior
- ...semiconductor design and verification through agentic AI... ...accelerates RTL design,... ...simulation, enabling engineers to achieve unprecedented... ...a highly capable Senior Design and Verification... ...and SystemVerilog/UVM testbenches used... ...verification coverage. Build reusable examples...SeniorShift work
- ...Fabric transport layer verification team is looking for a senior pre-silicon verification engineer to help verify our... ...Partner with architects, RTL, and firmware leads to... ...using SystemVerilog and UVM Solve complex,... ...Analyze functional and code coverage at a system level,...Senior
$145k - $234.5k
Senior ASIC Design Verification Engineer (Hardware) Senior ASIC Design Verification Engineer... ...write test plans, specify coverage, write tests, and debug. You... ...in SystemVerilog and UVM Required strengths Defining... ...ago Senior ASIC FrontEnd (RTL) Design Engineer Senior Mechanical...SeniorFull timeCasual workWork at office$150k - $250k
...overall quality of life. We are hiring FPGA Verification Engineers to build and maintain the verification infrastructure... ...avionics FPGA designs. You will develop UVM-based testbenches, create coverage-driven verification plans, and ensure RTL correctness for flight‑critical FPGA...Full timeWork at officeImmediate startVisa sponsorshipNight shift- ...in Mountain View is seeking a Senior Sales Recruiter. The ideal candidate... ...a strong understanding of FPGA design principles and... ...Verilog, and experience with verification tools. Applicants should hold a degree in electrical engineering or a related field and possess...SeniorContract work
- ...FPGA Design/Verification Engineer MUST CURRENTLY HOLD ACTIVE SECURITY CLEARANCE. The... ...engineer will be a verification UVM expert. This engineer will... ..., testbenches, tests and coverage. -Developing and finding... ...discipline collaboration with RTL Designers, Systems...
- A leading technology firm is looking for an FPGA Verification Engineer to join their team in Santa Clara, CA. You will be responsible for verifying complex FPGA designs and collaborating closely with design engineers to enhance product quality. The ideal candidate will...Senior
- Senior Sales Recruiter at AllianceIT Inc Mountain View... ...understanding of FPGA design principles and... ...in System Verilog and UVM verification methodology. Experience... ...). Knowledge of code coverage and functional coverage... ...degree in electrical engineering, Computer Engineering,...Contract work
- Intuitive in Sunnyvale, California is seeking an engineer to verify FPGA’s on da Vinci systems, ensuring functional correctness. You will write... ..., and work closely with design teams to enhance verification processes. The ideal candidate has advanced knowledge of HVL...Senior
- Mandatory Areas Must Have Skills - FPGA Verification Engineer Skill 1 - 8 + Years of in FPGA Skill 2 - 5 + Years of Exp in UVM Skill 2 - 5 + Years of Exp in SystemVerilog Location... ..., and corner cases. Perform code coverage and functional coverage analysis. Identify...Work at office
- ...block and full-chip verification environments using... .... Requires UVM, System Verilog, SVA... ...Develop test plans and coverage metrics from... ...C, SV, UVM. Debug RTL and Gate simulations... ...work with design engineers to verify fixes. Write... ...for validation of FPGA prototype (pre-...Senior
- NVIDIA AI is looking for a Formal Verification Engineer in Santa Clara, California. This role involves verifying GPU micro-architecture using formal verification tools, defining the verification scope, and delivering high-quality results efficiently. The ideal candidate...Senior
- ...We are seeking a Principal Design Verification Engineer to lead the verification of complex SoCs and... ...Responsibilities Develop and architect SystemVerilog/UVM-based verification environments. Create... ...constrained-random methodologies and coverage analysis. Develop, execute, and debug...Senior
- A technology company in Santa Clara is seeking an adaptive Design Verification Engineer to improve ASIC design verification processes. The ideal candidate has over 10 years of experience and expertise in C/C++, Verilog, and modern verification libraries. Responsibilities...SeniorContract work
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