Senior Design Verification Engineer

We are seeking a Principal Design Verification Engineer to lead the verification of complex SoCs and network switching solutions. This role involves developing advanced verification environments, driving verification methodologies, and collaborating closely with design teams to ensure high-quality silicon delivery. The position may also include technical leadership and project-level ownership of verification activities. Key Responsibilities Develop and architect SystemVerilog/UVM-based verification environments. Create detailed verification plans using constrained-random methodologies and coverage analysis. Develop, execute, and debug verification test cases to achieve coverage goals. Collaborate with design engineers to identify, troubleshoot, and resolve functional issues. Verify boot code and support validation of multi-core SoC architectures. Design and maintain software tools that improve verification efficiency and scalability. Perform regression testing and validation of verification tools and environments. Provide technical leadership and mentor verification engineers on project activities. Qualifications BS in Computer Engineering, Electrical Engineering, Computer Science, or related field with 10+ years of experience; or MS/PhD with 5+ years of relevant experience. Proven experience leading Design Verification activities for complex SoC projects. Successful track record of supporting SoC tape-outs under aggressive schedules. Strong analytical, debugging, and problem-solving skills. Ability to work effectively in a fast-paced, collaborative environment. Required Skills UVM (Universal Verification Methodology) Functional Verification & Coverage Analysis Verification Test Planning Python or Perl Scripting Object-Oriented Programming (OOP) C++ Programming ARM Assembly (Preferred) Networking Protocols (Preferred) Experience Required: 10+ Years #J-18808-Ljbffr