Senior Verification Engineer: SystemVerilog/UVM for SoC
iFlow Inc.
iFlow Inc. is seeking a Design Verification Engineer based in Santa Clara, CA, for a long-term position. The successful candidate will possess 8-15 years of experience, showcasing a strong proficiency in SystemVerilog and UVM, alongside debugging skills. Key responsibilities include developing verification environments for testing, performing coverage analysis, and collaborating with RTL designers to debug simulation failures while ensuring design quality across various domains. #J-18808-Ljbffr iFlow Inc.
Vacancy posted 1 day ago
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