Senior FPGA Verification Engineer — UVM & SystemVerilog
STI
STI is seeking a highly motivated FPGA Verification Engineer in Santa Clara, CA. In this role, you will develop verification plans for complex FPGA designs, ensuring functionality and reliability. You will collaborate closely with design engineers, execute verification plans, and maintain test benches using industry-standard methodologies. Candidates should possess a Bachelor's or Master's degree in Electrical Engineering, relevant experience, and strong communication skills. . #J-18808-Ljbffr STI
Vacancy posted 2 days ago
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