Senior SoC Verification Engineer — PCIe/UVM & IP
$119.8k - $258kSintegra Inc.
A technology company located in Mountain View, CA is seeking a Design Verification Engineer to support SoC-level verification of advanced high-speed and security IP. The role involves collaboration with design and architecture teams to verify complex digital systems. The ideal candidate will have over 5 years of SoC Design Verification experience and strong skills in SystemVerilog and UVM. This position offers a full-time employment opportunity with a salary range between $119,800 and $258,000. #J-18808-Ljbffr Sintegra Inc.
- ...self-motivated design verification engineer to join our growing team... ...you will be part of a SOC team to drive and improve... ...the next generation IP Maintain or improve current... .../System Verilog, UVM, C/C++, Scripting languages... ...protocols such as AXI, AHB, PCIE, DDR etc. will be an...Suggested
- ...the leading provider of SoC ASIC/FPGA and Embedded... ...SoC/ASIC RTL Design, UVM based verification, Emulation, FPGA based... ...We are looking for a Senior Design Verification who... ...plans for IP, subsystem, and SoC-level... ...collaborate with design engineers to resolve issues. Drive...Senior
- ...seeking a high‑impact Design Verification Engineer with strong technical depth... ...efforts across IP, subsystem and SoC levels. You will work in a... ...Development Develop robust UVM‑based testbench architectures... ...RTL, testbench, interfaces (PCIe/DDR/Ethernet) and system interactions...Senior
$2,000 per month
...staffed by leading engineers, Etched is redefining... ...are seeking a Design Verification Engineer to join our Interface IP DV team. You will... ...following IP subsystems: PCIe, Ethernet, CPU (arc/... ...and maintain UVM/SystemVerilog-based... ...with integration and SoC DV teams to validate...SuggestedWork at officeRelocation package$119.8k - $258k
...looking for a Design Verification Engineer to support SoC-level verification of... ...high-speed and security IP. This role involves... ...SystemVerilog and UVM Verify UCIe , Ethernet MAC & PCS , and PCIe designs Support PCIe... ...Verification experience Seniority Level Mid-Senior level...SuggestedFull time$138k - $317.8k
...Position Title: Principal, Design Verification Engineer, UAL and PCIe Subsystems (Confidential Client) Location... ...of state-of-the-art multi-core SoCs. Transforming the requirements from... .... Experience with System Verilog, UVM. Experience with writing a detailed...Permanent employment- ...for an experienced design verification engineer to join our SoC team at Baidu’s Sunnyvale office... ...level. You will help on UVM Testbench development,... ...using Verilog models of analog IP. Develop testbench, test cases... ...on either one aspect (PCIe, Ethernet, HBM, GDDR, DDR,...Work at office
- ...We are seeking a Principal Design Verification Engineer to lead the verification of complex SoCs and network switching solutions. This role involves developing advanced... ...Develop and architect SystemVerilog/UVM-based verification environments. Create detailed verification...Senior
- ...Hi, Title: Lead / Senior Verification engineer Location: San Jose, CA / Santa Clara,... ...Months Rate: $Open Skills: UVM and System Verilog Requirement... ...years of proven experience on ASIC / SoC / IP Verification. • Strong experience in...Senior
- ...for internal and external SoC projects Provide domain-... ...coordinate validation, verification, and integration flows across multiple IPs, including checkpoints... ...s, or PhD in Electrical Engineering, Computer Engineering, or... ...skills in SystemVerilog, UVM, and C/C++ for test...SeniorNight shift
- ...you could accomplish. Design Verification Engineers at Apple are responsible for... ...performance of Apple's premier SOCs. This is a critical job... ...the quality of the SOC or an IP or subsystem. This requires you... ...verification methodologies like UVM + Experience with C/C++, assembly...
$175k - $215k
...will report to a Silicon Engineering Lead. Responsibilities... ..., scalable verification plans Drive the development... ...third‑party Verification IP (VIP) to accelerate the... ...complex testbenches using UVM/SystemVerilog Proven track... ...interfaces such as PCIe Gen 5/6, DDR5, or Ethernet...$97.7k - $182.62k
...poster from Capgemini Engineering About the Job You're Considering... ...team as a Design Verification Engineer, contributing... ...System-on-Chip (SoC) designs that integrate... ...using SystemVerilog and UVM for IP and SoC designs.... ..., experience, skills, seniority, performance, sales or...16 hoursFull timeLocal area- ...Architect block and full-chip verification environments using HVLs and constrained... ...random techniques for SOCs with embedded CPUs and mixed signal interfaces. Requires UVM, System Verilog, SVA. Develop... ...simulations and work with design engineers to verify fixes. Write...Senior
- ...apply for the Design Verification Engineer role at Quest... ...functional correctness of SoC, contributing to a... ...in block/IP/sub‑system level verification... ...such as PCIe (preferably Gen‑6)... ...Experience coding UVM SoC/sub‑system level... ...transportation arrangements. Seniority Level Mid‑Senior...Full time
- ...worldwide. **Description** As a Design Verification Engineer, you'll be at the center of our... ...RF link controllers for Apple's SOCs, you'll craft highly reusable UVM verification environments that set... ...that thoroughly validate complex IP and subsystem designs, working closely...WorldwideNight shift
- ...beyond. Together, we advance your career. The Role As a Senior CPU Design Verification Engineer, you will join a CPU testbench infrastructure team responsible... ...tests and components using C++, SystemVerilog, and UVM Collaborate with design, verification, and debug teams...Senior
$130k - $160k
...Team Credo is seeking a Design Verification Engineer to ensure the quality and performance of complex... ...reusable testbenches, write SV‑UVM sequences, debug issues, and collaborate... ...testbenches and write test sequences. Verify PCIe subsystems and other interfaces (I2C/I3...Senior$185k - $230k
...CXL®, Ethernet, NVLink, PCIe®, and UALink™... ...seeking a Principal Design Verification Engineer with strong problem-solving... ...success of cutting-edge SoC designs. Key Responsibilities... ...using SystemVerilog/UVM and other relevant... ...third-party Verification IP for protocols such as...Full timeFlexible hoursNight shift$200k - $320k
...for a experienced Design Verification engineer with at least 5 years of pre... ...verification for complex IP, subsystems, and/or SoC system level verification... ...functional closure. This is a senior individual-contributor... ...perspectives ~ Well-versed in UVM methodology and testbench...H1bVisa sponsorshipWork visaFlexible hoursNight shift$2,000 per month
...tier investors and staffed by leading engineers, Etched is redefining the... ...Summary We are seeking a Design Verification Engineer to join our Internal IP DV team. You will ensure the custom... ...responsibilities Develop and maintain UVM/SystemVerilog testbenches for high-...Work at officeRelocation packageNight shift$120k - $225k
...Description We’re hiring experienced Design Verification Engineers to play a key role in developing and... ..., architecture modeling, custom analog IP, compiler, emulation, and post-silicon teams... ...development and execution using UVM or other advanced DV methodologies. Creation...Senior- ...interconnects to scalable photonic engines, Lumilens is unlocking... ...chiplet — building UVM testbenches, writing... ...closure. Guided by the verification plan and methodology,... ...). 3+ years of ASIC/SoC functional verification... ...) verification . UCIe, PCIe/CXL, Ethernet, or UALink...
- ...companies and thriving start-ups in need of Verification Engineers. Lets talk about what you want next!... ...of customers quickly. What does our SOC DV team do? Well, we're verifying high... ...asic verification environments such as UVM and System Verilog will come a long way...Relocation package
$141.3k - $226k
...silicon division, working on IPs for ASIC products such... ...for IP and subsystem verification, including SerDes and... ...in‑depth knowledge in UVM, SystemVerilog, RTL design... ...Bachelor in Electrical Engineering, Computer Science or... ...of proven experience in SoC/ASIC verification or...$80 - $90 per hour
...adaptive, self-motivative Design Verification Engineer to join our growing team. As... ...delivers Industry leading IP and help our experts in RTL,... ...verification libraries like UVM • 10+years of ASIC design... ...engineering/Electrical Engineering Seniority level Seniority level Not...16 hoursContract work- ...Location: San Jose, CA Looking for engineers with strong protocol expertise to verify industry-standard interface IPs such as PCIe, DDR, Ethernet, USB, etc Key Responsibilitie s:... ...USB/Ethe rnet)Expertise in SystemVerilog, UVM, and VIP integr ationExperience with protocol...
- ...Responsibilities Develop FPGA Design Verification tests, and test plans... ...bug reports Work with IP vendors and Design engineers to resolve bugs Desired Skills... ...in system Verilog, and UVM Strong experience in software... ...with Protocols and VIPs for PCIe, Ethernet, DRAM Ability to...
- ...POSITION: Senior DV Engineer Who We Are: Quest Global delivers world-class end-to-... ...and executing end-to-end design verification activities for IP, Subsystem, or SoC-level projects. This role involves... ...Express etc. ○ Strong in HVL (UVM / SystemVerilog / OVM), C/C++, Perl...Remote work
$87.4k - $132k
...Position: Design Verification Engineer (eInfochips Inc) Job Description: What... ...You'll Be Doing: Strong SV/UVM expertise AXI/NOC/Ethernet/PCIe/UCIe Switch expertise is needed... ...Verification Environment for ASIC SoC and providing verification support...Hourly payFull timeTemporary workWork experience placementWork at officeNight shift
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