Sign up to access all features of our service.
  • Job search
  • Favorites
  • Create a CV
    New
  • Salaries
  • Subscriptions

Principal, Design Verification Engineer, UAL and PCIe Subsystems

$138k - $317.8k

YK Solutions LLC

Position Title: Principal, Design Verification Engineer, UAL and PCIe Subsystems (Confidential Client)
Location: Santa Clara, CA | Onsite
Employment Type: Permanent

Compensation

  • Salary: $138,000 - $317,800/yr
  • Bonus: Base, bonus, RSU, refresher RSUs

Position Summary

As part of the Design Verification Team at Our Client, you will verify all of the circuitry that goes inside chips for the general market and for specific customers. These chips use cutting-edge technology to facilitate data transfers at high speeds, and you will help verify that each design meets customer specifications whether they are a major telecom organization or automotive company, etc.

In this role, you will develop the architecture for a functional verification environment, including reference models and bus-functional monitors and drivers and contribute to the methodology behind such development.

Primary Functions

  • Writing a verification test plan using random techniques and coverage analysis and working with designers to ensure it is complete.
  • Developing tests and tuning the environment to achieve coverage goals. Debugging failures and working with designers to resolve issues.
  • Verifying boot code and architecting, developing, and maintaining tools to streamline the design of state-of-the-art multi-core SoCs.
  • Transforming the requirements from the engineering teams into software tools that are both easy to use and scalable within a highly parallel compute environment.
  • Unit and regression testing of software tools.

Must-Haves

  • BS/MS/PhD in Computer Science, Electrical Engineering, or Computer Engineering, 10-12 years of relevant professional experience.
  • Experience with System Verilog, UVM.
  • Experience with writing a detailed test plan and building a sophisticated, directed, random-verification environment.
  • Experience with scripting language such as Python or Perl and EDA Verification tools.
  • Experience with Object-Oriented Design and implementation.
  • Good understanding of Linux O.S.
  • Good programming skills desired, especially C++ and ARM assembly.
  • Prior working knowledge of UAL or PCIe protocols.
  • Diligent, detail-oriented, and willing to take initiative and handle assignments with minimal supervision.
  • Requires the ability to accept and work with differing opinions.
  • Cannot be a close-minded developer.
  • Must be able to learn on the fly and work in a fast-paced environment.
Vacancy posted a month ago
Similar jobs that could be interesting for youBased on the Principal, Design Verification Engineer, UAL and PCIe Subsystems in Santa Clara, CA vacancy
  • $200k - $250k

    Job Title: Principal Design Verification Engineer - PCIe / High-Speed SoCLocation: Santa Clara, CACompensation: $200K - $250K base DOE plus bonus and RSUs...  ...verification strategy and plans for PCIe IP, SerDes subsystems, and high-speed SoC integrations to achieve tape-out... 
    Principal

    CyberCoders

    Santa Clara, CA
    3 days ago
  •  ...Experience: 5-12+ Years Responsibilities Verify CPU subsystem and standard interfaces using SystemVerilog/UVM. Develop verification plans, UVM testbenches, test cases,...  ...exception handling. Execute regressions, debug RTL/design issues, and drive functional and code... 
    Suggested

    ACL Digital

    San Jose, CA
    5 days ago
  • $200k - $250k

    Job Title: Principal RTL Design Engineer - PCIe / CXL / High-Speed SoCLocation: Santa Clara, CACompensation...  ...timing closure.Work closely with the verification team on pre-silicon activities,...  ...debug skills are essential.Define subsystem microarchitecture and register specifications... 
    Principal

    CyberCoders

    Santa Clara, CA
    3 days ago
  • $105k - $260k

     ...performance RISC-V CPUs on the planet—designed for data center, AI, and...  ...to work alongside engineers who built iconic processors...  ...YouTubePrincipal CPU Design Verification Engineer:We are seeking an experienced...  ...of complex CPU and related subsystems based on the open-source... 
    Principal
    Contract work
    Work at office

    Ventana Micro Systems

    Cupertino, CA
    4 days ago
  •  ...PERSON:We are seeking a high‑impact Design Verification Engineer with strong technical depth, ownership...  ...leading verification efforts across IP, subsystem, and SoC levels.You will work in a...  ...failures across RTL, testbench, interfaces (PCIe/DDR/Ethernet), and system... 
    Suggested

    AMD

    Santa Clara, CA
    4 days ago
  • $158.6k - $237.6k

     ...thrive, learn, and lead. Your Team, Your ImpactAs part of the Design Verification Team at Marvell, you will verify all of the circuitry that...  ...multi-core SoCs.• Transforming the requirements from the engineering teams into software tools that are both easy to use and scalable... 
    Principal
    Permanent employment
    Internship
    Work from home

    Marvell

    Santa Clara, CA
    3 days ago
  • $164.47k - $311.89k

     ...About the RoleIntel is seeking a Senior Design Verification Engineer for the Silicon Chassis team. In this...  ..., protocol verification, and memory subsystem behavior, with enough breadth in RTL,...  ...such as AMBA (CHI, ACE, AXI), PCIe, UCIe, and CXL; cache coherency and memory... 
    Full time
    Internship
    Local area
    Immediate start
    Shift work

    Intel

    Santa Clara, CA
    4 days ago
  • $141.91k - $200.34k

     ...:Job Description: Intel is seeking a Design Verification Engineer for the Silicon Chassis team. In this...  ...interconnect and chassis IP/features at IP and subsystem level- Build reusable verification...  ...for example AMBA AXI/ACE/CHI, PCIe, CXL, UCIe- Understanding of cache coherency... 
    Full time
    Local area
    Immediate start
    Shift work

    Intel

    Santa Clara, CA
    4 days ago
  • $142.8k - $274.8k

     ...Hardware, and Infrastructure Engineering (SCHIE) is the team...  ...SCHIE is responsible for design, development, manufacturing...  ...infrastructure.We are looking for a Principal Silicon Design Verification Engineer to join the team...  ...test content at the subsystem and SoC levels, including... 
    Principal
    Ongoing contract
    Permanent employment
    Work at office
    Local area
    Worldwide
    3 days per week

    Microsoft

    Mountain View, CA
    4 days ago
  • $163k - $237k

    Lead the PCIe microarchitecture and RTL development...  ...high-performance designs that strictly adhere to...  ...to integrate the PCIe subsystem, ensuring it meets chip...  ...goals.Coordinate with Verification and Physical Design teams...  ...degree in Electrical Engineering, Computer Engineering,... 
    Worldwide

    Google

    Sunnyvale, CA
    1 day ago
  • $154.68k - $231.7k

     ...from architecture and design all the way through layout...  ...ramp up.The SubSystem Physical Implementation...  ...with Senior and Junior engineers to deliver reference floorplan...  ...teams, including RTL, verification, and CAD, to ensure...  ...cores, memory, PCIE/CXL highly preferredEthernet... 
    Principal
    Permanent employment
    Full time
    Internship
    Work from home
    Relocation

    Marvell

    Santa Clara, CA
    6 days ago
  • $210k - $355k

     ...actively developing the technologies to make this possible, with the ultimate goal of enabling human life on Mars.PRINCIPAL DESIGN VERIFICATION ENGINEER (SILICON ENGINEERING)At SpaceX we’re leveraging our experience in building rockets and spacecraft to deploy Starlink... 
    Principal
    Permanent employment
    Temporary work
    Worldwide
    Weekend work

    SpaceX

    Palo Alto, CA
    5 days ago
  •  ...Together, we advance your career. THE ROLE: As a Senior CPU Design Verification Engineer, you will join a CPU testbench infrastructure team...  ...by core verification and debug teams to validate complex subsystems, working closely with globally distributed engineering teams... 

    AMD

    Santa Clara, CA
    6 days ago
  • $124k - $208.4k

     ...Come build with us!Role and ResponsibilitiesAs a Senior GPU Design Verification Engineer - GCDV, you will contribute to the verification of top-...  ...Samsung’s mobile GPU through three levels: Graphic Code, Subsystem Verification, and Formal Verification. As a... 
    Hourly pay
    Full time
    Relocation

    Samsung Semiconductor

    San Jose, CA
    3 days ago
  • $167.7k - $245.2k

     ...Because full product development—from design to qualification to production—is within...  ...more, and work quickly. As an ASIC Design Verification Engineer, you will play a critical role in...  ...Preferred Qualifications: · Experience in PCIe and AXI protocol· Experience with Linux... 
    Full time
    Temporary work
    Local area
    Flexible hours

    CISCO Systems

    San Jose, CA
    21 hours ago
  • $141.91k - $200.34k

     ...on earth. We work every single day to design and manufacture silicon products that empower...  ...us to do something wonderful.As an IP Verification Engineer, you will be working on UCIe Mixed-...  ...Signal VerificationExperience with UCIe or PCIe or I/OJob Type:Experienced HireShift:... 
    Full time
    Work experience placement
    Local area
    Immediate start
    Shift work

    Intel

    Santa Clara, CA
    1 day ago
  • $180.2k - $297.2k

     ...and ResponsibilitiesWe are seeking a highly skilled GPU Design Verification Engineer (GCDV) to join our team at SARC/ACL. As a key member of our...  ...Samsung’s mobile GPU through three levels: Graphic Code, Subsystem Verification, and Formal Verification. As a... 
    Hourly pay
    Full time
    Relocation

    Samsung Semiconductor

    San Jose, CA
    1 day ago
  •  ...silicon and system.DescriptionWe are looking for an experienced design verification engineer to join our SoC team at Baidu’s Sunnyvale office. The...  ...preference.SoC and IP verification experience on either one aspect (PCIe, Ethernet, HBM, GDDR, DDR, MMU, Cache).Familiar with C/C++.... 
    Work at office

    Baidu

    Sunnyvale, CA
    1 day ago
  •  ...WiproContact: Meghana GorusuCompany: SRI Tech SolutionsJob Title:Design Verification EngineerLcation: Sunnyvale CA /Redmond WA/ Austin TX Onsite...  ...UVM/System Verilog-based verification environments for IP/subsystem/SoC level testing· Develop directed and random testcases,... 
    Full time
    For contractors
    Remote work

    SRI Tech

    Sunnyvale, CA
    4 days ago
  •  ...computing, cloud, and AI. Whether you’re designing next-gen processors, enabling AI...  ...for an adaptive, self-motivated design verification engineer to join our growing team. As a key contributor...  ...standard protocols such as AXI, AHB, PCIE, DDR etc. will be an advantageACADEMIC... 

    AMD

    San Jose, CA
    1 day ago
  • $151k - $251.8k

     ...world. Come build with us!Role and ResponsibilitiesAs a Design Verification Engineer, you will contribute to the verification of System IP, including...  ...semiconductor products, enabling cutting-edge memory subsystem capabilities across diverse market segments.Joining our... 
    Hourly pay
    Full time
    Relocation

    Samsung Semiconductor

    San Jose, CA
    4 days ago
  • $142.8k - $274.8k

     ...MicrosoftOverviewMicrosoft Silicon, Cloud Hardware, and Infrastructure Engineering (SCHIE) is the team behind Microsoft’s expanding Cloud...  ...changes our world. The AI Silicon Engineering (AISiE) SoC Design Verification team is seeking passionate, driven, and intellectually... 
    Principal
    Ongoing contract
    Permanent employment
    Work at office
    Local area
    Worldwide
    3 days per week

    Microsoft

    Mountain View, CA
    4 days ago
  •  ...ROLE: In this role, you will drive the verification of new and existing features for AMD’s...  ...strategies across complex digital subsystems, working closely with cross-functional engineering teams to deliver robust, bug-free designs. THE PERSON:  You are passionate about... 

    AMD

    San Jose, CA
    1 day ago
  • $115k - $268k

     ...of one of the most exciting semiconductor startups in the industry. We are hiring multiple Design Verification engineers to advance our innovative RISC-V processors and subsystems. Role: Develop and execute verification plans for units and features. Build testbenches,... 
    Contract work

    Ventana Micro Systems

    Cupertino, CA
    5 days ago
  • $214.1k - $309.8k

     ...revolutionary solutions for data centers by designing some of the most complex chips being...  ...the world!Your Impact:As an ASIC Design Verification Leader, you will play a pivotal role in...  ...domain experience on one or more protocols - PCIe, Ethernet, RDMA, TCP, Fiber Channel (FC)... 
    Full time
    Temporary work
    Local area
    Flexible hours

    CISCO Systems

    San Jose, CA
    21 hours ago
  • $180k - $230k

     ...We are looking for talented engineers and leaders who have an entrepreneurial...  ...and want to drive their design from concept to silicon to...  .... Summary: As a Senior ASIC Verification Engineer, you will be responsible...  ...Switching, TCP/IP, security, PCIe and other industry standard... 
    Flexible hours

    Ethernovia

    San Jose, CA
    2 days ago
  •  ...Position: Design Verification Engineer (eInfochips Inc) Job Description: WhatYou'llBeDoing: Strong SV/UVM expertise AXI/NOC/Ethernet/PCIe/UCIe Switch expertise is needed CPU ARM/RISC-V with C knowledge Regression & Coverage Closure What We Are Looking For: Responsible... 
    Hourly pay
    Full time
    Temporary work
    Work experience placement
    Night shift

    Arrow ECS

    San Jose, CA
    4 days ago
  • $130k - $192k

     ...Semiconductor Recruiting. Functional verification of complex designs. Responsible for verification from...  .../ controller sub-systems, Ethernet/PCIE/CXL (Physical coding sublayer)/Serdes...  ...Full-time Job function Job function Engineering and Design Industries Semiconductor... 
    Full time
    H1b

    Tara Technical Solutions (TTS)

    San Jose, CA
    5 days ago
  •  ...that team there's no telling what you could accomplish. Design Verification Engineers at Apple are responsible for verifying the functionality...  ...model). You own ensuring the quality of the SOC or an IP or subsystem. This requires you to review design and architecture... 

    Apple

    Santa Clara, CA
    3 days ago
  •  ...communication for millions of users worldwide. **Description** As a Design Verification Engineer, you'll be at the center of our silicon design group's...  ...test cases that thoroughly validate complex IP and subsystem designs, working closely with multi-functional teams... 
    Worldwide
    Night shift

    Apple

    Sunnyvale, CA
    1 day ago

Do you want to receive more vacancies?

Subscribe and receive similar vacancies to Principal, Design Verification Engineer, UAL and PCIe Subsystems. Be the first to apply!